MC68LK332ACAG16 Freescale Semiconductor, MC68LK332ACAG16 Datasheet - Page 33

IC MCU 32BIT LV AMASK 144-LQFP

MC68LK332ACAG16

Manufacturer Part Number
MC68LK332ACAG16
Description
IC MCU 32BIT LV AMASK 144-LQFP
Manufacturer
Freescale Semiconductor
Series
M683xxr
Datasheets

Specifications of MC68LK332ACAG16

Core Processor
CPU32
Core Size
32-Bit
Speed
16.78MHz
Connectivity
EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
15
Program Memory Type
ROMless
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
M683xx
Core
CPU32
Data Bus Width
32 bit
Maximum Clock Frequency
16 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Interface Type
QSPI, SCI, UART
Minimum Operating Temperature
- 40 C
No. Of I/o's
15
Ram Memory Size
2KB
Cpu Speed
16MHz
No. Of Timers
16
Embedded Interface Type
QSPI, SCI, UART
Digital Ic Case Style
LQFP
Rohs Compliant
Yes
Data Ram Size
2 KB
Number Of Programmable I/os
15
Number Of Timers
16
Cpu Family
68K/M683xx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Program Memory Size
Not Required
Total Internal Ram Size
2KB
# I/os (max)
15
Number Of Timers - General Purpose
16
Operating Supply Voltage (typ)
5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Quantity
Price
Part Number:
MC68LK332ACAG16
Manufacturer:
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Part Number:
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Manufacturer:
Freescale Semiconductor
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3.5.3 Base Address Registers
CSBARBT — Chip-Select Base Address Register Boot ROM
CSBAR[10:0] —Chip-Select Base Address Registers
ADDR[23:11] — Base Address Field
BLKSZ — Block Size Field
3.5.4 Option Registers
MC68332
MC68332TS/D
RESET:
RESET:
ADDR
ADDR
15
23
15
23
0
0
A base address is the starting address for the block enabled by a given chip select. Block size deter-
mines the extent of the block above the base address. Each chip select has an associated base register
so that an efficient address map can be constructed for each application. If a chip-select base address
register is programmed with the same address as a microcontroller module or memory array, an access
to that address goes to the module or array and the chip-select signal is not asserted.
This field sets the starting address of a particular address space. The address compare logic uses only
the most significant bits to match an address within a block. The value of the base address must be a
multiple of block size. Base address register diagrams show how base register bits correspond to ad-
dress lines.
This field determines the size of the block that must be enabled by the chip select. The following table
shows bit encoding for the base address registers block size field.
The option registers contain eight fields that determine timing of and conditions for assertion of chip-
select signals. For a chip-select signal to be asserted, all bits in the base address register must match
the corresponding internal upper address lines, and all conditions specified in the option register must
be satisfied. These conditions also apply to providing DSACK or autovector support.
ADDR
ADDR
14
22
14
22
0
0
ADDR
ADDR
13
21
13
21
0
0
Block Size Field
ADDR
ADDR
12
20
12
20
0
0
000
001
010
011
100
101
110
111
Freescale Semiconductor, Inc.
ADDR
ADDR
11
19
11
19
0
For More Information On This Product,
0
ADDR
ADDR
10
18
10
18
0
0
Go to: www.freescale.com
ADDR
ADDR
17
17
0
9
0
9
Block Size
128 K
256 K
512 K
16 K
64 K
1 M
2 K
8 K
ADDR
ADDR
16
16
0
8
0
8
ADDR
ADDR
15
15
0
7
0
7
Address Lines Compared
ADDR
ADDR
14
14
0
6
0
6
ADDR[23:11]
ADDR[23:13]
ADDR[23:14]
ADDR[23:16]
ADDR[23:17]
ADDR[23:18]
ADDR[23:19]
ADDR[23:20]
ADDR
ADDR
13
13
0
5
0
5
ADDR
ADDR
12
12
0
4
0
4
ADDR
ADDR
11
11
0
3
0
3
$YFFA4C–$YFFA74
0
2
1
2
MOTOROLA
BLKSZ
BLKSZ
0
$YFFA48
1
0
0
1
0
33

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