MC68LK332ACAG16 Freescale Semiconductor, MC68LK332ACAG16 Datasheet - Page 84

• Manufacturer Part Number: MC68LK332ACAG16
• Description: IC MCU 32BIT LV AMASK 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68LK332ACAG16

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 16.78MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Interface Type: QSPI, SCI, UART
• Minimum Operating Temperature: - 40 C
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 16
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Data Ram Size: 2 KB
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 2KB
• # I/os (max): 15
• Number Of Timers - General Purpose: 16
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7 Standby RAM with TPU Emulation RAM
7.1 Overview
7.2 TPURAM Register Block
7.3 TPURAM Registers
TRAMMCR —TPURAM Module Configuration Register
TSTOP —Stop Control
84
MOTOROLA
RESET:
STOP
15
0
The TPURAM module contains a 2-Kbyte array of fast (two bus cycle) static RAM, which is especially
useful for system stacks and variable storage. Alternately, it can be used by the TPU as emulation RAM
for new timer algorithms.
The TPURAM can be mapped to any 4-Kbyte boundary in the address map, but must not overlap the
module control registers. (Overlap makes the registers inaccessible.) Data can be read or written in
bytes, word, or long words. TPURAM responds to both program and data space accesses. Data can be
read or written in bytes, words, or long words. The TPURAM is powered by V
During power-down, the TPURAM contents are maintained by power on standby voltage pin V
Power switching between sources is automatic.
Access to the TPURAM array is controlled by the RASP field in TRAMMCR. This field can be encoded
so that TPURAM responds to both program and data space accesses. This allows code to be executed
from TPURAM, and permits the use of program counter relative addressing mode for operand fetches
from the array.
An address map of the TPURAM control registers follows. All TPURAM control registers are located in
supervisor data space.
There are three TPURAM control registers: the RAM module configuration register (TRAMMCR), the
RAM test register (TRAMTST), and the RAM array base address registers (TRAMBAR).
There is an 8-byte minimum register block size for the module. Unimplemented register addresses are
read as zeros, and writes have no effect.
This bit controls whether the RAM array is in stop mode or normal operation. Reset state is zero, for
normal operation. In stop mode, the array retains its contents, but cannot be read or written by the CPU.
Y = M111, where M is the logic state of the MM bit in the SIMCR.
Access
0 = RAM array operates normally.
1 = RAM array enters low-power stop mode.
14
S
S
S
0
0
13
0
0
$YFFB06–
$YFFB00
$YFFB02
$YFFB04
$YFFB3F
Address
12
0
0
Table 28 TPURAM Control Register Address Map
Freescale Semiconductor, Inc.
11
For More Information On This Product,
0
0
15
TPURAM MODULE CONFIGURATION REGISTER (TRAMMCR)
10
0
0
Go to: www.freescale.com
TPURAM BASE ADDRESS REGISTER (TRAMBAR)
9
0
0
TPURAM TEST REGISTER (TRAMTST)
RASP
8
1
7
NOT USED
8 7
NOT USED
DD
in normal operation.
MC68332TS/D
$YFFB00
MC68332
0
STBY
0
.