MC68LK332ACAG16 Freescale Semiconductor, MC68LK332ACAG16 Datasheet - Page 85

• Manufacturer Part Number: MC68LK332ACAG16
• Description: IC MCU 32BIT LV AMASK 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68LK332ACAG16

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 16.78MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Interface Type: QSPI, SCI, UART
• Minimum Operating Temperature: - 40 C
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 16MHz
• No. Of Timers: 16
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Data Ram Size: 2 KB
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 2KB
• # I/os (max): 15
• Number Of Timers - General Purpose: 16
• Operating Supply Voltage (typ): 5V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TRAMBAR — TPURAM Base Address and Status Register
RASP — RAM Array Space Field
TRAMTST — TPURAM Test Register
ADDR[23:11] — RAM Array Base Address
RAMDS — RAM Array Disable
7.4 TPURAM Operation
MC68332
MC68332TS/D
RESET:
ADDR
15
23
0
TRAMTST is used for factory testing of the TPURAM module.
These bits specify address lines ADDR[23:11] of the base address of the RAM array when enabled.
The RAM array is disabled by internal logic after a master reset. Writing a valid base address to the
RAM array base address field (bits [15:3]) automatically clears RAMDS, enabling the RAM array.
There are six TPURAM operating modes, as follows:
0 = TPURAM array is placed in unrestricted space
1 = TPURAM array is placed in supervisor space
0 = RAM array is enabled
1 = RAM array is disabled
1. The TPURAM module is in normal mode when powered by V
2. Standby mode is intended to preserve TPURAM contents when V
3. Reset mode allows the CPU to complete the current bus cycle before resetting. When a syn-
4. Test mode functions in conjunction with the SIM test functions. Test mode is used during factory
5. Writing the STOP bit of TRAMMCR causes the TPURAM module to enter stop mode. The
6. The TPURAM array may be used to emulate the microcode ROM in the TPU module. This pro-
ADDR
14
22
0
by byte, word, or long word. A byte or aligned word (high-order byte is at an even address) ac-
cess only takes one bus cycle or two system clocks. A long word or misaligned word access
requires two bus cycles.
contents are maintained by V
of V
is not guaranteed.
chronous reset occurs while a byte or word TPURAM access is in progress, the access will be
completed. If reset occurs during the first word access of a long-word operation, only the first
word access will be completed. If reset occurs during the second word access of a long word
operation, the entire access will be completed. Data being read from or written to the RAM may
be corrupted by asynchronous reset.
test of the MCU.
TPURAM array is disabled (which allows external logic to decode TPURAM addresses, if nec-
essary), but all data is retained. If V
switches to V
vides a means of developing custom TPU code. The TPU selects TPU emulation mode. While
in TPU emulation mode, the access timing of the TPURAM module matches the timing of the
TPU microinstruction ROM to ensure accurate emulation. Normal accesses via the IMB are in-
hibited and the control registers have no effect, allowing external RAM to emulate the TPURAM
at the same addresses.
ADDR
DD
13
21
0
or V
ADDR
12
20
STBY
0
STBY
Freescale Semiconductor, Inc.
ADDR
with no loss of data. When TPURAM is powered by V
11
19
0
, as in standby mode. Stop mode is exited by clearing the STOP bit.
For More Information On This Product,
ADDR
10
18
0
Go to: www.freescale.com
STBY
ADDR
17
9
0
. Circuitry within the TPURAM module switches to the higher
ADDR
DD
16
8
0
falls below V
ADDR
15
7
0
ADDR
14
6
0
STBY
ADDR
13
5
0
during stop mode, internal circuitry
ADDR
DD
12
4
0
. The array can be accessed
DD
ADDR
STBY
11
3
0
is removed. TPURAM
, access to the array
NOT USED
2
0
MOTOROLA
1
0
$YFFB04
$YFFB02
RAMDS
0
0
85