DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 1395

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

26.3.7
RAMCR is an 8-bit readable/writable register that enables/disables the access to the on-chip
RAM.
Bit
7 to 5
4
3 to 0
RAM Control Register (RAMCR)
Bit Name

RAME

Initial value:
Initial
Value
All 0
1
All 0
R/W:
Bit:
R
7
0
-
R/W
R
R/W
R
R
6
0
-
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
RAM Enable
This bit enables/disables the on-chip RAM.
0: On-chip RAM disabled
1: On-chip RAM enabled
When this bit is cleared to 0, the access to the on-chip
RAM is disabled. In this case, an undefined value is
returned when reading or fetching the data or
instruction from the on-chip RAM, and writing to the on-
chip RAM is ignored.
When RAME is cleared to 0 to disable the on-chip
RAM, an instruction to access the on-chip RAM should
not be set next to the instruction to write RAMCR. If
such an instruction is set, normal access is not
guaranteed.
When RAME is set to 1 to enable the on-chip RAM, an
instruction to read RAMCR should be set next to the
instruction to write to RAMCR. If an instruction to
access the on-chip RAM is set next to the instruction to
write to RAMCR, normal access is not guaranteed.
Reserved
These bits are always read as 0. The write value should
always be 0.
R
5
0
-
RAME
R/W
4
1
R
3
0
-
Rev. 3.00 May 17, 2007 Page 1337 of 1582
R
2
0
-
R
1
0
-
Section 26 Power-Down Modes
R
0
0
-
REJ09B0181-0300