DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 206

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 7 User Break Controller (UBC)
7.3.10
BBRB is a 16-bit readable/writable register, which specifies (1) bus master for I bus cycle, (2) L
bus cycle or I bus cycle, (3) instruction fetch or data access, (4) read or write, and (5) operand size
in the break conditions of channel B.
Initial value:
Rev. 3.00 May 17, 2007 Page 148 of 1582
REJ09B0181-0300
Bit
15 to 11
10
9
8
7
6
Note:
R/W:
Bit:
*
These bits are reserved in the mask ROM and ROM-less versions. These bits are always read as 0.
The write value should always be 0.
Break Bus Cycle Register B (BBRB)
15
R
0
Bit Name

CPB2*
CPB1*
CPB0*
CDB1*
CDB0
-
14
R
0
-
13
R
0
-
Initial
Value
All 0
0
0
0
0
0
12
R
0
-
11
R
0
-
R/W
R
R/W
R/W
R/W
R/W
R/W
CPB2* CPB1* CPB0* CDB1* CDB0
R/W
10
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
L Bus Cycle/I Bus Cycle Select B
Select the L bus cycle or I bus cycle as the bus cycle
of the channel B break condition.
00: Condition comparison is not performed
01: The break condition is the L bus cycle
10: The break condition is the I bus cycle
11: The break condition is the L bus cycle
Bus Master Select B for I Bus
Select the bus master when the I bus is selected as
the bus cycle of the channel B break condition.
However, when the L bus is selected as the bus cycle,
the setting of the CPB2 to CPB0 bits is disabled.
000: Condition comparison is not performed
xx1: The CPU cycle is included in the break condition
x1x: The DMAC cycle is included in the break condition
1xx: The DTC cycle is included in the break condition
9
0
R/W
8
0
R/W
7
0
R/W
6
0
IDB1*
R/W
5
0
R/W
IDB0
4
0
RWB1* RWB0 SZB1* SZB0*
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0