DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 247

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

8.5
There are three transfer modes: normal, repeat, and block transfer modes. Since transfer
information is in the data area, it is possible to transfer data over any required number of channels.
When activated, the DTC reads transfer information stored in the data are and transfers data
according to the transfer information. After the data transfer is complete, it writes updated transfer
information back to the data area.
The DTC specifies the source address and destination address in SAR and DAR, respectively.
After a transfer, SAR and DAR are incremented, decremented, or fixed independently.
Table 8.3 shows the DTC transfer modes.
Table 8.3
Notes: 1. Either source or destination is specified to repeat area.
Setting the CHNE bit in MRB to 1 makes it possible to perform a number of transfers with a
single activation (chain transfer). Setting the CHNS bit in MRB to 1 can also be made to have
chain transfer performed only when the transfer counter value is 0.
Figure 8.4 shows a flowchart of DTC operation, and table 8.4 summarizes the conditions for DTC
transfers including chain transfer (combinations for performing the second and third transfers are
omitted).
Transfer
Mode
Normal
Repeat*
Block*
2
2. Either source or destination is specified to block area.
3. After transfer of the specified transfer count, initial state is recovered to continue the
4. Number of transfers of the specified block size of data.
1
Operation
operation.
Size of Data Transferred at One
Transfer Request
1 byte/word/longword
1 byte/word/longword
Block size specified by CRAH (1
to 256 bytes/words/longwords)
DTC Transfer Modes
Memory Address Increment or
Decrement
Incremented/decremented by 1, 2, or
4, or fixed
Incremented/decremented by 1, 2, or
4, or fixed
Incremented/decremented by 1, 2, or
4, or fixed
Rev. 3.00 May 17, 2007 Page 189 of 1582
Section 8 Data Transfer Controller (DTC)
REJ09B0181-0300
Transfer
Count
1 to 65536
1 to 256*
1 to 65536*
3
4