DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 322

IC SUPERH MCU FLASH 112LQFP

DF70845AD80FPV

Manufacturer Part Number
DF70845AD80FPV
Description
IC SUPERH MCU FLASH 112LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7080r
Datasheet

Specifications of DF70845AD80FPV

Core Size
32-Bit
Program Memory Size
512KB (512K x 8)
Core Processor
SH-2
Speed
80MHz
Connectivity
EBI/EMI, FIFO, I²C, SCI, SSU
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
76
Ram Memory Size
32KB
Cpu Speed
80MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V, 4.5V To 5.5V
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF70845AD80FPV
Manufacturer:
TAIYO
Quantity:
40 000
Part Number:
DF70845AD80FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 9 Bus State Controller (BSC)
Rev. 3.00 May 17, 2007 Page 264 of 1582
REJ09B0181-0300
Bit
21, 20
19 to 15
14 to 11
Bit Name
SA[1:0]
TED[3:0]
Initial
Value
00
All 0
0000
R/W
R/W
R
R/W
Description
Space Attribute Specification
Selects memory card interface or I/O card interface
when PCMCIA interface is selected.
SA1:
0: Selects memory card interface for the space for A25
1: Selects I/O card interface for the space for A25 = 1.
SA0:
0: Selects memory card interface for the space for A25
1: Selects I/O card interface for the space for A25 = 0.
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Delay Cycles from Address Output to RD
and WE Assertion
Specify the number of delay cycles from address output
to RD and WE assertion in PCMCIA interface.
0000: 0.5 cycle
0001: 1.5 cycles
0010: 2.5 cycles
0011: 3.5 cycles
0100: 4.5 cycle
0101: 5.5 cycles
0110: 6.5 cycles
0111: 7.5 cycles
1000: 8.5 cycle
1001: 9.5 cycles
1010: 10.5 cycles
1011: 11.5 cycles
1100: 12.5 cycle
1101: 13.5 cycles
1110: 14.5 cycles
1111: 15.5 cycles
= 1.
= 0.

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