DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 438

• Manufacturer Part Number: DF70845AD80FPV
• Description: IC SUPERH MCU FLASH 112LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7080r

Specifications of DF70845AD80FPV

• Core Size: 32-Bit
• Program Memory Size: 512KB (512K x 8)
• Core Processor: SH-2
• Speed: 80MHz
• Connectivity: EBI/EMI, FIFO, I²C, SCI, SSU
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 76
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 3V To 3.6V, 4.5V To 5.5V
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 9 Bus State Controller (BSC)
9.5.17
Table 9.36 shows the number of cycles required for access to the external memory by the CPU. As
the table shows, the number of cycles varies with the clock ratio, the access size, the external bus
width of the LSI, and the setting for wait insertion. For details on the wait-insertion setting, see
section 9.4, Register Descriptions.
Table 9.36 Number of External Access Cycles
Note: n:
Synchronous logic and a layered bus structure have been adopted for this LSI circuit. Data on each
bus are input and output in synchronization with rising edges of the corresponding clock signal.
The L bus and I bus are synchronized with the Iφ and Bφ clocks, respectively. Figure 9.54 shows
an example of the timing of write access to a word of data over the external bus, with a bus-width
of 8 bits, when Iφ:Bφ = 2:1. Once the CPU has output the data to the L bus, data are transferred to
the I bus in synchronization with rising edges of Bφ. There are two Iφ clock cycles in a single Bφ
clock cycle when Iφ: Bφ = 2:1. Thus, when Iφ: Bφ = 2:1, data transfer from the L bus to the I bus
Rev. 3.00 May 17, 2007 Page 380 of 1582
REJ09B0181-0300
External
Bus Width
8 bits
16 bits
32 bits
m, o:
Access to External Memory by CPU
Access
Size
Byte
Word
Longword
Byte/Word
Longword
Byte/Word/
Longword
When Iφ:Bφ = 8:1, n = 0 to 7.
When Iφ:Bφ = 4:1, n = 0 to 3.
When Iφ:Bφ = 3:1, n = 0 to 2.
When Iφ:Bφ = 2:1, n = 0 to 1.
When Iφ:Bφ = 1:1, n = 0.
m: Wait setting, o: Wait setting + idle setting
For details, see section 9.4, Register Descriptions.
Write/Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Number of Access Cycles
(1 + n) × Iφ + (3 + m) × Bφ
(1 + n) × Iφ + (3 + m) × Bφ + 1 × Iφ
(1 + n) × Iφ + (3 + m) × Bφ + 1 × (2 + o) × Bφ
(1 + n) × Iφ + (3 + m) × Bφ + 1 × (2 + o) × Bφ + 1 × Iφ
(1 + n) × Iφ + (3 + m) × Bφ + 3 × (2 + o) × Bφ
(1 + n) × Iφ + (3 + m) × Bφ + 3 × (2 + o) × Bφ + 1 × Iφ
(1 + n) × Iφ + (3 + m) × Bφ
(1 + n) × Iφ + (3 + m) × Bφ + 1 × Iφ
(1 + n) × Iφ + (3 + m) × Bφ + 1 × (2 + o) × Bφ
(1 + n) × Iφ + (3 + m) × Bφ + 1 × (2 + o) × Bφ + 1 × Iφ
(1 + n) × Iφ + (3 + m) × Bφ
(1 + n) × Iφ + (3 + m) × Bφ + 1 × Iφ