DF70845AD80FPV Renesas Electronics America, DF70845AD80FPV Datasheet - Page 899
DF70845AD80FPV
Manufacturer Part Number
DF70845AD80FPV
Description
IC SUPERH MCU FLASH 112LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7080r
Datasheet
1.DF70844AD80FPV.pdf
(1644 pages)
Specifications of DF70845AD80FPV
Core Size
32-Bit
Program Memory Size
512KB (512K x 8)
Core Processor
SH-2
Speed
80MHz
Connectivity
EBI/EMI, FIFO, I²C, SCI, SSU
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
112-LQFP
No. Of I/o's
76
Ram Memory Size
32KB
Cpu Speed
80MHz
Digital Ic Case Style
LQFP
Supply Voltage Range
3V To 3.6V, 4.5V To 5.5V
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
R0K570865S001BE - KIT STARTER FOR SH7086R0K570865S000BE - KIT STARTER FOR SH7086HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF70845AD80FPV
Manufacturer:
TAIYO
Quantity:
40 000
Company:
Part Number:
DF70845AD80FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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5. When modem control is enabled, the RTS signal is output depending on the empty status of
SCFRDR. When RTS is 0, reception is possible. When RTS is 1, this indicates that the
SCFRDR is full and no extra data can be received.
Figure 16.10 shows an example of the operation when modem control is used.
Serial
data
RDF
FER
Serial data
RXD
RTS
1
Figure 16.10 Example of Operation Using Modem Control (RTS)
Start
bit
Start
bit
0
0
D0
Figure 16.9 Example of SCIF Receive Operation
D0
D1 D2
One frame
D1
(8-Bit Data, Parity, One Stop Bit)
Data
D7
D7 0/1
RXIF interrupt
request
Parity
bit
Parity
bit
0/1
Section 16 Serial Communication Interface with FIFO (SCIF)
Stop
bit
1
Stop
bit
1
Start
bit
0
Data read and RDF flag
read as 1 then cleared to
0 by RXIF interrupt handler
D0
D1
Rev. 3.00 May 17, 2007 Page 841 of 1582
Data
Start
bit
0
D0
D7
Parity
bit
D1
0/1
Stop
bit
ERIF interrupt request
generated by receive
error
1
D7 0/1
Idle state
(mark state)
REJ09B0181-0300
1
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