HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 149
HD6417708SF60V
Manufacturer Part Number
HD6417708SF60V
Description
IC SUPERH MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417708SF60V.pdf
(635 pages)
Specifications of HD6417708SF60V
Core Processor
SH-2
Core Size
32-Bit
Speed
60MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417708SF60V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417708SF60V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Bits 5 and 4—Instruction Fetch/Data Access Select A (IDA1 and IDA0): These bits select whether
to break channel A on instruction fetch and/or data access cycles.
Bit 5: IDA1
0
1
Bits 3 and 2—Read/Write Select A (RWA1 and RWA0): These bits select whether to break
channel A on read and/or write cycles.
Bit 3: RWA1
0
1
Bits 1 and 0—Operand Size Select A (SZA1 and SZA0): These bits select the bus cycle operand
size as a channel A break condition.
Bit 1: SZA1
0
1
7.2.8
BBRB is the break bus cycle register for channel B. The bit configuration is the same as for
BBRA.
Break Bus Cycle Register B (BBRB)
Bit 4: IDA0
0
1
0
1
Bit 2: RWA0
0
1
0
1
Bit 0: SZA0
0
1
0
1
Description
No conditions compared
Break on instruction fetch cycle
Break on data access cycle
Break on either instruction fetch or data access cycle
Description
No conditions compared
Break on read cycles
Break on write cycles
Break on both read and write cycles
Description
Operand size is not a break condition
Break on byte access
Break on word access
Break on longword access
(Initial value)
(Initial value)
(Initial value)
129
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