HD6417708SF60V Renesas Electronics America, HD6417708SF60V Datasheet - Page 201
HD6417708SF60V
Manufacturer Part Number
HD6417708SF60V
Description
IC SUPERH MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.HD6417708SF60V.pdf
(635 pages)
Specifications of HD6417708SF60V
Core Processor
SH-2
Core Size
32-Bit
Speed
60MHz
Connectivity
EBI/EMI, SCI, SmartCard
Peripherals
POR, WDT
Number Of I /o
8
Program Memory Type
ROMless
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Ram Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417708SF60V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417708SF60V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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9.10
9.10.1
The WDT can be used to cancel standby mode with an NMI or other interrupts. The procedure is
described below. (The WDT does not run when resets are used for canceling, so keep the RESET
pin low until the clock stabilizes.)
1. Before transitioning to standby mode, always clear the TME bit in WTCSR to 0. When the
2. Set the type of count clock used in the CKS2–CKS0 bits in WTCSR and the initial values for
3. Move to standby mode by executing a SLEEP instruction to stop the clock.
4. The WDT starts counting by detecting the edge change of the NMI signal or detecting
5. When the WDT count overflows, the CPG starts supplying the clock and the processor
6. The counter stops at the values H'00–H'01. The stop value depends on the clock ratio.
9.10.2
To change the frequency used by the PLL, use the WDT. When changing the frequency only by
switching the divider, do not use the WDT.
1. Before changing the frequency, always clear the TME bit in WTCSR to 0. When the TME bit
2. Set the type of count clock used in the CKS2–CKS0 bits of WTCSR and the initial values for
3. When the frequency control register (FRQCR) is written, the clock stops and the processor
4. When the WDT count overflows, the CPG resumes supplying the clock and the processor
5. The counter stops at the values H'00–H'01. The stop value depends on the clock ratio.
TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count
overflows.
the counter in the WTCNT counter. These values should ensure that the time till count
overflow is longer than the clock oscillation settling time.
interrupts.
resumes operation. The WOVF flag in WTCSR is not set when this happens.
is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows.
the counter in the WTCNT counter. These values should ensure that the time till count
overflow is longer than the clock oscillation settling time.
enters standby mode temporarily. The WDT starts counting.
resumes operation. The WOVF flag in WTCSR is not set when this happens.
Using the WDT
Canceling Standbys
Changing the Frequency
181
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