DF61543J40FPV Renesas Electronics America, DF61543J40FPV Datasheet - Page 93

• Manufacturer Part Number: DF61543J40FPV
• Description: IC H8SX/1543 MCU FLASH 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1500r

Specifications of DF61543J40FPV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SCI, SSU
• Peripherals: DMA, Motor Control PWM, PWM, WDT
• Number Of I /o: 95
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: R0K561582S000BE - KIT DEV RSK H8SX/1582F
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Oscillator Type: -

Table 2.6
Instruction
ADD
SUB
ADDX
SUBX
INC
DEC
ADDS
SUBS
DAA
DAS
MULXU
MULU
MULU/U
MULXS
MULS
MULS/U
Arithmetic Operation Instructions
Size
B/W/L
B/W/L
B/W/L
L
B
B/W
W/L
L
B/W
W/L
L
Function
(EAd) ± #IMM → (EAd), (EAd) ± (EAs) → (EAd)
Performs addition or subtraction on data between immediate data,
general registers, and memory. Immediate byte data cannot be
subtracted from byte data in a general register.
(EAd) ± #IMM ± C → (EAd), (EAd) ± (EAs) ± C → (EAd)
Performs addition or subtraction with carry on data between immediate
data, general registers, and memory. The addressing mode which
specifies a memory location can be specified as register indirect with
post-decrement or register indirect.
Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2. (Byte operands
can be incremented or decremented by 1 only.)
Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a general register.
Rd (decimal adjust) → Rd
Decimal-adjusts an addition or subtraction result in a general register by
referring to the CCR to produce 2-digit 4-bit BCD data.
Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers: either 8
bits × 8 bits → 16 bits, or 16 bits × 16 bits → 32 bits.
Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers: either 8
bits × 8 bits → 16 bits, or 16 bits × 16 bits → 32 bits.
Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers (32 bits
× 32 bits → upper 32 bits).
Rd × Rs → Rd
Performs signed multiplication on data in two general registers: either 8
bits × 8 bits → 16 bits, or 16 bits × 16 bits → 32 bits.
Rd × Rs → Rd
Performs signed multiplication on data in two general registers: either 16
bits × 16 bits → 16 bits, or 32 bits × 32 bits → 32 bits.
Rd × Rs → Rd
Performs signed multiplication on data in two general registers (32 bits ×
32 bits → upper 32 bits).
Rev. 3.00 Sep. 24, 2009 Page 45 of 916
REJ09B0381-0300
Section 2 CPU