M30833FJGP#U5 Renesas Electronics America, M30833FJGP#U5 Datasheet - Page 129
M30833FJGP#U5
Manufacturer Part Number
M30833FJGP#U5
Description
IC M32C/83 MCU FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30833FJGPU3.pdf
(96 pages)
3.M30833FJGPU3.pdf
(529 pages)
Specifications of M30833FJGP#U5
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30833FJGP#U5M30833FJGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R
R
M
e
E
3
. v
J
Figure 10.9 Interrupt Priority Level Select Circuit
2
0
Low
1
9
C
3 .
High
B
Peripheral Function Interrupt Priority
(if priority levels are the same)
8 /
0
1
3
0
3
J
G
Bus Conflict/Start, Stop Condition(
4
a
0 -
n
o r
UART0 Transmission/NACK
UART1 Transmission/NACK
UART2 Transmission/NACK
UART3 Transmission/NACK
Each Interrupt Priority Level
3 .
UART0 Reception/ACK
UART2 Reception/ACK
Bus Conflict/Start, Stop
Bus Conflict/Start, Stop
1
UART1 Reception/ACK
UART3 Reception/ACK
UART4 Reception/ACK
u
UART4 Transmission/
Condition(UART1,4)
, 1
3
Condition(UART2)
p
A/D1 Converter
1
2
(
UART0,3)
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
Timer B3
Timer B4
Timer B5
M
0
DMA0
DMA1
DMA2
DMA3
NACK
INT5
INT4
INT3
INT2
INT1
INT0
0
3
6
2
C
8 /
Page 104
, 3
M
3
2
C
f o
Level 0 (initial value)
8 /
4
3
8
) T
8
Each Interrupt Priority Level
Intelligent I/O Interrupt 11
Intelligent I/O Interrupt 0
Intelligent I/O Interrupt 3
Intelligent I/O Interrupt 4
Intelligent I/O Interrupt 5
Intelligent I/O Interrupt 6
Intelligent I/O Interrupt 7
Intelligent I/O Interrupt 8
Intelligent I/O Interrupt 10
Intelligent I/O Interrupt 1
Intelligent I/O Interrupt 2
Intelligent I/O Interrupt 9
Oscillation Stop Detect
RLVL2 to RLVL0 Bits
Key Input Interrupt
Watchdog Timer,
A/D0 Converter
Address Match
/CAN Interrupt 2
/CAN Interrupt 0
/CAN Interrupt 1
DMAC II
I Flag
Reset
NMI
IPL
Interrupt
request is
acknowledged.
To CLK
Interrupt
request is
acknowledged.
To CPU
10. Interrupts
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