M30833FJGP#U5 Renesas Electronics America, M30833FJGP#U5 Datasheet - Page 226
M30833FJGP#U5
Manufacturer Part Number
M30833FJGP#U5
Description
IC M32C/83 MCU FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30833FJGPU3.pdf
(96 pages)
3.M30833FJGPU3.pdf
(529 pages)
Specifications of M30833FJGP#U5
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30833FJGP#U5M30833FJGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M
e
E
3
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J
Table 16.18 STSPSEL Bit Function
Figure 16.22 STSPSEL Bit Function
2
0
16.3.2 Start Condition or Stop Condition Output
1
9
C
Start condition and stop condition
output
Timing to generate a start condition
and stop condition interrupt request
3 .
B
8 /
The start condition is generated when the STAREQ bit in the UiSMR4 register (i=0 to 4) is set to "1"
(start). The restart condition is generated when the RSTAREQ bit in the UiSMR4 register is set to "1"
(start). The stop condition is generated when the STPREQ bit in the UiSMR4 is set to "1" (start).
The start condition is output when the STAREQ bit is set to "1" and the STSPSEL bit in the UiSMR4
register is set to "1" (start or stop condition generation circuit selected). The restart condition is output
when the RSTAREQ bit and STSPSEL bit are set to "1". The stop condition is output when the STPREQ
bit and the STSPSEL bit are set to "1".
When the start condition, stop condition or restart condition is output, do not generate an interrupt be-
tween the instruction to set the STAREQ bit, STPREQ bit or RSTAREQ bit to "1" and the instruction to set
the STSPSEL bit to "1". When the start condition is output, set the STAREQ bit to "1" before the
STSPSEL bit is set to "1".
Table 16.18 lists function of the STSPSEL bit. Figure 16.22 shows functions of the STSPSEL bit.
0
1
3
0
3
J
G
4
a
0 -
n
o r
3 .
1
u
, 1
3
p
1
Setting value of
the STSPEL bit
2
(
Function
M
0
0
(1) In slave mode,
(1) In master mode,
3
6
SCLi
SCLi
SDAi
i=0 to 4
SDAi
2
C
CKDIR is set to "1" (external clock)
STSPSEL is set to "0" (no start condition and stop condition output)
CKDIR is set to "0" (internal clock)
STSPSEL is set to "1" (start condition and stop condition output)
Page 201
8 /
, 3
M
STAREQ=1
(start)
3
2
C
0
f o
8 /
Start condition detect
interrupt
4
3
8
) T
8
Start condition detect
interrupt
1
Program with a port determines
how the start condition or stop
condition is output
The start condition and stop
condition are detected
STSPSEL = 0
0
STPREQ=1
(start)
Stop condition detect
interrupt
The STAREQ bit, RSTAREQ bit and
STPREQ bit determine how the start
condition or stop condition is output
Start condition and stop condition
generation are completed
Stop condition detect
interrupt
16. Serial I/O (Special Function)
1
STSPSEL = 1
0
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