M30833FJGP#U5 Renesas Electronics America, M30833FJGP#U5 Datasheet - Page 277
M30833FJGP#U5
Manufacturer Part Number
M30833FJGP#U5
Description
IC M32C/83 MCU FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30833FJGPU3.pdf
(96 pages)
3.M30833FJGPU3.pdf
(529 pages)
Specifications of M30833FJGP#U5
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30833FJGP#U5M30833FJGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Figure 21.4 Intelligent I/O Group 3 Block Diagram
1
9
C
3 .
B
8 /
0
1
Request from communication function
ISCLK3
3
0
ISRxD3
BT3S
BTS
f
1
3
J
G
4
a
BCK1 to BCK0
0 -
11
n
o r
(1)
3 .
1
u
, 1
3
p
1
Request from group2
2
(
M
0
0
3
6
2
NOTES:
selector
C
Clock
1. In the 100-pin package, these pins are not connected to external pins.
2. Each register enters a reset state after the G3BCR0 register supplies the
Page 252
8 /
Transmit operation clock
Receive operation clock
clock.
Reset
DIV4 to DIV0
by 2(n+1)
, 3
Divider
M
3
2
C
Request by matching the base
timer with the G3PO0 register
f
BT3
f o
8 /
Group3 base
timer reset
4
3
8
G3PO0 register
G3PO1 register
G3PO2 register
G3PO3 register
G3PO4 register
G3PO5 register
G3PO6 register
G3PO7 register
) T
Base timer
8
G3MK4 register
G3MK5 register
G3MK6 register
G3MK7 register
Transmission
Reception
G3TB register
Polarity
inverse
IPOL
Overflow of the bit 15
in the base timer
Base timer interrupt request (BT3R)
Mode controller
Shift counter
Receive shift
register
Bit modulation
Bit modulation
Bit modulation
Bit modulation
Bit modulation
Bit modulation
Bit modulation
Bit modulation
Mode controller
Transmit Shift
Shift counter
register
PWM
PWM
PWM
PWM
PWM
PWM
PWM
PWM
DIV4 to DIV0, BCK1 to BCK0 : Bits in the G3BCR0 register
BTS : Bit in the G3BCR1 register
BT3S : Bit in the BTSR register
MOD2 to MOD0 : Bits in the G3POCRj register (j = 0 to 7)
OPOL, IPOL : Bits in the G3CR register
Real time port
output value
Polarity
inverse
(3)
OPOL
control
control
control
control
output
output
output
output
PWM
PWM
PWM
PWM
G3RB register
000 to 010, 100
000 to 010,
100
MOD2 to MOD0
MOD2 to MOD0
111
OUTC3
OUTC3
OUTC3
OUTC3
OUTC3
OUTC3
111
(PO3jR)
Waveform generation
interrupt request
(SIO3RR)
Receive interrupt
request
(SIO3TR)
Transmit interrupt
request
2
3
4
5
6
7
OUTC3
OUTC3
(3)
21. Intelligent I/O
(3)
(3)
(Note 1)
0
1
/ISTxD3
/ISCLK3
(1)
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