M30833FJFP#U5 Renesas Electronics America, M30833FJFP#U5 Datasheet - Page 381
M30833FJFP#U5
Manufacturer Part Number
M30833FJFP#U5
Description
IC M32C/83 MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30833FJGPU3.pdf
(96 pages)
3.M30833FJGPU3.pdf
(529 pages)
Specifications of M30833FJFP#U5
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-QFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30833FJFP#U5M30833FJFP#U3
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
M30833FJFP#U5M30833FJFP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R
R
M
e
E
3
. v
J
Figure 22.28 Example of CAN Data Frame Transmit Operation
Figure 22.29 Example of CAN Data Frame Receive Operation
2
0
22.2.3 CAN Receive Timing
1
9
C
3 .
B
Figure 22.29 shows an operation example of when the CAN receives a frame.
8 /
0
1
3
0
(1) When the RECREQ bit in the C0MCTLi register (i=0 to 15) is set to "1" (receive requested), the
(2) When the CAN starts receiving the frame, the RECSTATE bit in the C0STR register is set to "1"
(3) After the CAN frame reception is completed, the INVALDTA bit in the C0MCTLi register is set to
(4) After data is written to the message slot, the INVALDATA bit is set to "0" (stops receiving) and the
3
J
G
4
a
NEWDATA bit
INVALDATA bit
RECSUCC bit
SISi bit
CAN bus
RECREQ bit
MBOX3 -
MBOX0 bits
RECSTATE bit
i = 0 to 15
0 -
n
o r
CAN bus
TRMSUCC bit
TRMSTATE bit
SISi bit
SENTDATA bit
TRMACTIVE bit
TRMREQ bit
MBOX3 -
MBOX0 bits
i = 0 to 15
CAN is ready to receive the frame at anytime.
(during reception).
"1" (storing received data), the NEWDATA bit in the C0MCTLi register is set to "1" (receive com-
plete) and the RECSUCC bit in the C0STR register is set to "1" (reception completed).
SISi bit is set to "1" (interrupt requested). The MBOX3 to MBOX0 bits store received message slot
numbers.
3 .
1
u
, 1
3
p
1
2
(
M
0
0
3
6
2
C
Page 356
8 /
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
, 3
Bus idle
M
Bus idle
3
(1)
Start transmtting
2
C
f o
8 /
Set to "1" by program
simultaneously
4
Start receiving
(2)
3
8
(1)
) T
8
Set to "1" by program
simultaneously
Receive frame
Transmit frame
Receive frame
Transmit frame
Reception completed
Transmission completed
(3)
(2)
(4)
Transmission-completed
message slot number
Intermission field
Reception-completed
message slot number
Intermission field
Bus idle
Bus idle
22. CAN Module
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