M30833FJFP#U5 Renesas Electronics America, M30833FJFP#U5 Datasheet - Page 8
M30833FJFP#U5
Manufacturer Part Number
M30833FJFP#U5
Description
IC M32C/83 MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30833FJGPU3.pdf
(96 pages)
3.M30833FJGPU3.pdf
(529 pages)
Specifications of M30833FJFP#U5
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-QFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30833FJFP#U5M30833FJFP#U3
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
M30833FJFP#U5M30833FJFP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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7. Bus................................................................................... 52
8. Clock Generation Circuit _______________________ 65
9. Protection ___________________________________ 88
A-2
6.2 Setting Processor Mode .......................................................................................... 48
7.1 Bus Settings ............................................................................................................. 52
7.2 Bus Control ............................................................................................................... 55
8.1 Types of Clock Generation Circuits........................................................................ 65
8.2 CPU Clock and BCLK .............................................................................................. 79
8.3 Peripheral Function Clock ....................................................................................... 79
8.4 Clock Output Function ............................................................................................ 80
8.5 Power Consumption Control .................................................................................. 80
6.2.1 Applying VSS to CNVSS Pin ............................................................................ 48
6.2.2 Applying VCC to CNVSS Pin ............................................................................ 48
7.1.1 Selecting External Address Bus ...................................................................... 53
7.1.2 Selecting External Data Bus ............................................................................ 53
7.1.3 Selecting Separate/Multiplexed Bus ............................................................... 53
7.2.1 Address Bus and Data Bus .............................................................................. 55
7.2.2 Chip-Select Signal ............................................................................................ 55
7.2.3 Read and Write Signals ..................................................................................... 57
7.2.4 Bus Timing ......................................................................................................... 58
7.2.5 ALE Signal ......................................................................................................... 62
7.2.6 RDY Signal ......................................................................................................... 62
7.2.7 HOLD Signal ...................................................................................................... 63
7.2.8 External Bus State when Accessing Internal Space...................................... 64
7.2.9 BCLK Output ..................................................................................................... 64
7.2.10 DRAM Control Signals (RAS, CASL, CASH and DW) .................................. 64
8.1.1 Main Clock ......................................................................................................... 74
8.1.2 Sub Clock .......................................................................................................... 75
8.1.3 On-chip Oscillator Clock .................................................................................. 76
8.1.4 PLL Clock .......................................................................................................... 77
8.3.1 f
8.3.2 f
8.3.3 fC
8.5.1 Normal Operation Mode ................................................................................... 81
8.5.2 Wait Mode .......................................................................................................... 82
8.5.3 Stop Mode .......................................................................................................... 84
_______
_________
1
AD ....................................................................................................................................................
, f
32 ..................................................................................................................................................
8
, f
32
and f
2n .........................................................................................................................
_______
__________
__________
_____
79
79
80
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