M30833FJFP#U5 Renesas Electronics America, M30833FJFP#U5 Datasheet - Page 93
M30833FJFP#U5
Manufacturer Part Number
M30833FJFP#U5
Description
IC M32C/83 MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30833FJGPU3.pdf
(96 pages)
3.M30833FJGPU3.pdf
(529 pages)
Specifications of M30833FJFP#U5
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-QFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30833FJFP#U5M30833FJFP#U3
Manufacturer:
Renesas Electronics America
Quantity:
135
Part Number:
M30833FJFP#U5M30833FJFP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R
R
M
e
E
3
. v
J
Figure 8.3 CM1 Register
2
0
1
C
9
3 .
B
8 /
0
1
3
0
3
J
G
4
a
0 -
o r
n
System Clock Control Register 1
b7
3 .
1
NOTES:
u
3
, 1
p
b6
0
1
1. Rewrite the CM1 register after the PRC0 bit in the PRCR register is set to "1" (write enable).
2. When the CM10 bit is set to "1", X
3. When the CM10 bit is set to "1", the MCD register is set to "08
4. CM17 bit is enabled only when the CM21 bit in the CM2 register is set to "0". Use the procedure
(
2
M
X
CM20 bit is set to "1" (oscillation stop detect function enabled) or the CM21 bit to "1" (on-chip
oscillator selected), do not set the CM10 bit to "1".
shown in Figure 8.13 to set the CM17 bit to "1".
0
b5
1
0
IN
3
6
2
, X
b4
0
C
CIN
8 /
b3
0
Page 68
, 3
and X
b2
0
M
b1
0
3
COUT
2
C
b0
f o
8 /
are placed in high-impedance states.
4
(b4 - b1)
3
8
Symbol
CM10
CM17
) T
8
(b5)
(b6)
Bit
Symbol
CM1
All Clock Stop
Control Bit
Reserved Bit
Reserved Bit
Reserved Bit
CPU Clock Select
Bit 2
OUT
(4)
becomes "H" and the internal feedback resistance is disabled.
Bit Name
(2)
(1)
Address
0007
16
0 : Clock oscillates
1 : All clocks stop (stop mode)
Set to "0"
Set to "1"
Set to "0"
0 : Main clock
1 : PLL clock
16
" (divide-by-8 mode). When the
After Reset
0010 0000
Function
2
8. Clock Generation Circuit
(3)
RW
RW
RW
RW
RW
RW
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