M30833FJFP#U3 Renesas Electronics America, M30833FJFP#U3 Datasheet - Page 198
M30833FJFP#U3
Manufacturer Part Number
M30833FJFP#U3
Description
IC M32C/83 MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30833FJGPU3.pdf
(96 pages)
3.M30833FJGPU3.pdf
(529 pages)
Specifications of M30833FJFP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Part Number
Manufacturer
Quantity
Price
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R
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3
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Figure 16.1 UARTi Block Diagram
2
0
1
9
C
3 .
B
8 /
RxDi
0
1
3
0
CTSi / RTSi
3
J
G
4
a
0 -
n
o r
RxDi
Selecting Clock Source
CLKi
3 .
1
SP
u
SP: Stop bit
PAR: Parity bit
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: Bits in UiMR register
CLK1 to CLK0, CKPOL, CRD, CRS: Bits in UiC0 register
UiERE: Bit in UiC1 register
i=0 to 4
f
f
f
, 1
3
SP
2n
1
8
p
1
(2)
CLK1 to CLK0
2
(
Inverse Circuit
10
M
01
00
0
STPS
2SP
RxD Data
1SP
1
1
Switching
0
CKPOL
Polarity
0
SP
Circuit
3
CLK
6
2
Switching Circuit
0
C
STPS
1SP
1
RxD Polarity
2SP
0
SP
8 /
Page 173
CRS 0
1
0
CTS/RTS
selected
, 3
CKDIR
Inside
Outside
0
PAR
Clock Synchronous Type
(when internal clock is selected)
0
1
M
PAR
Vss
Inverse
IOPOL
No inverse
1
3
0
0
1
PRYE
PAR
enabled
PAR
disabled
2
1
0
CRD
PAR
enabled
PRYE
PAR
disabled
0
1
C
1 / (m+1)
f o
0
Register
CTS/RTS disabled
UiBRG
8 /
0
CTS/RTS disabled
4
Clock
Asynchronous Type
3
Clock
Synchronous
Type
8
SMD2 to SMD0
Clock
Asynchronous
Type
SMD2 to SMD0
) T
Clock
Synchronous
Type
8
CRD
1
0
Clock Synchronous Type
Clock Synchronous Type
0
1/16
1/16
Clock Asynchronous
1/2
Clock Synchronous
Type
(when external clock is
selected)
010, 100, 101, 110
Clock Synchronous Type
(when internal clock is selected)
Clock Asynchronous
Receive
010, 100, 101, 110
Clock
Asynchronous
Type (9 bits)
Clock
Asynchronous
Type (9 bits)
0
Clock
Asynchronous
Type (7 bits)
Clock
Asynchronous
Type (8 bits)
Clock
Synchronous Type
CTSi
Clock
Asynchronous
Type (7 bits)
Clock
Asynchronous
Type (8 bits)
Clock
Synchronous Type
0
0
1
Transmit
1
D
D
8
RTSi
8
m : setting value of UiBRG register
NOTES:
001
001
1. P7
2. The CNT3 to CNT0 bits in the TCSPR register select no division
Clock
Synchronous Type
Clock
Synchronous Type
Clock
Asynchronous
Type (8 bits)
Clock
Asynchronous
Type (9 bits)
Clock
Asynchronous
Type (8 bits)
Clock
Asynchronous
Type (9 bits)
0
1
SMD2 to SMD0
not for the CMOS output.
(n=0) or divide-by-2n (n=1 to 15).
CKDIR
0
Clock
Asynchronous
Type (7 bits)
and P7
0
0
1
1
D
D
Clock
Asynchronous
Type (7 bits)
7
7
UiERE
Logic Inverse Circuit + MSB/LSB Conversion Circuit
Logic Inverse Circuit + MSB/LSB Conversion Circuit
High-order bits of data bus
Low-order bits of data bus
1
Control Circuit
Control Circuit
Error Signal Output
disable
Error Signal Output
enable
are ports for the N-channel open drain output, but
D
D
Transmit
6
6
Receive
0
1
D
D
Output Circuit
Error Signal
5
5
D
D
4
4
Receive
Clock
UARTi Transmit Register
Transmit
Clock
UARTi Receive Register
D
D
IOPOL
3
3
Inverse
0
1
D
D
Transmit/
2
2
No inverse
Receive
Inverse Circuit
Unit
TxD Data
D
D
1
1
D
D
0
0
Switching
Polarity
(Note 1)
Circuit
TxD
UiRB Register
UiTB Register
TxDi
16. Serial I/O
TxDi
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