M30833FJFP#U3 Renesas Electronics America, M30833FJFP#U3 Datasheet - Page 220
M30833FJFP#U3
Manufacturer Part Number
M30833FJFP#U3
Description
IC M32C/83 MCU FLASH 100QFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30833FJGPU3.pdf
(96 pages)
3.M30833FJGPU3.pdf
(529 pages)
Specifications of M30833FJFP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-QFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R
R
M
e
E
16.3 Special Mode 1 (I
3
. v
J
Table 16.12 I
2
0
I
cations of I
Figure 16.19 shows a block diagram of I
register and interrupts. Tables 16.14 to 16.16 list pin settings.
As shown in Table 16.14, I
"010
and stabilizes due to a SDAi output via the delay circuit.
Interrupt
1
9
C
Selectable Function
2
3 .
B
C mode is a mode to communicate with external devices with a simplified I
8 /
0
1
3
0
2
3
J
" and the IICM bit in the UiMR register is set to "1". SDAi output changes after SCLi becomes low ("L")
G
4
a
0 -
Item
n
o r
3 .
1
u
, 1
3
p
2
1
C mode. Table 16.13 lists registers to be used and settings, Table 16.14 lists each function.
2
(
2
M
0
C Mode Specifications
0
3
6
2
C
Page 195
8 /
, 3
Start condition detect, stop condition detect, no acknowledgment detect, acknowledgment
detect
• Clock phase setting
• Arbitration lost
• SDAi digital delay
M
Selected from clock delay or no clock delay.
Refer to 16.3.4 Transfer Clock.
The update timing of the ABT bit in the UiRB register can be selected.
Refer to 16.3.3 Arbitration.
Selected from no digital delay or 2 to 8 cycle delay of the count source of BRG.
Refer to 16.3.5 SDA Output.
2
3
C Mode)
2
2
C mode is entered when the SMD2 to SMD0 bits in the UiMR register is set to
C
f o
8 /
4
3
8
) T
8
2
C mode. Figure 16.20 shows timings for transfer to the UiRB
Specifications
16. Serial I/O (Special Function)
2
C . Table 16.12 lists specifi-
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