D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 1006
D6417760BP200ADV
Manufacturer Part Number
D6417760BP200ADV
Description
IC SUPER H MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D6417760BP200ADV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417760BP200ADV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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25.3.9
HACRSR is a 32-bit read/write register that indicates the status of the HAC RX controller.
Writing 0 to the bit will initialize it.
Initial value:
Initial value:
Rev. 2.00 Feb. 12, 2010 Page 922 of 1330
REJ09B0554-0200
Bit
21
20
19
18 to 14 ⎯
13
12
11 to 0
Bit
31 to 23 ⎯
R/W:
R/W:
Bit:
Bit:
Bit Name
STDRYIE
PLRFRQIE
PRRFRQIE
PLRFOVIE
PRRFOVIE
⎯
RX Status Register (HACRSR)
Bit Name
31
15
R
R
-
0
0
-
30
14
R
-
R
0
0
-
R/W
FOV
PLR
29
13
R
0
0
-
All 0
Initial Value
Initial Value
0
0
0
All 0
0
0
All 0
R/W
PRR
FOV
28
12
R
0
0
-
27
11
R
R
0
0
-
-
R/W*
R
26
10
R
R
0
-
0
R/W
R/W
R/W
R/W
R
R/W
R/W
R
-
25
R
R
-
0
9
0
-
Description
0: Disables status data ready interrupts.
1: Enables status data ready interrupts.
0: Disables PCML RX request interrupts.
1: Enables PCML RX request interrupts.
0: Disables PCMR RX request interrupts.
1: Enables PCMR RX request interrupts.
Reserved
Always 0 for read and write.
PCML RX Overrun Interrupt Enable
0: Disables PCML RX overrun interrupts.
1: Enables PCML RX overrun interrupts.
0: Disables PCMR RX overrun interrupts.
1: Enables PCMR RX overrun interrupts.
Reserved
Always 0 for read and write.
Description
Reserved
Always 0 for read and write.
Status Data Ready Interrupt Enable
PCML RX Request Interrupt Enable
PCMR RX Request Interrupt Enable
PCMR RX Overrun Interrupt Enable
24
R
R
-
0
8
0
-
23
-
R
R
0
7
0
-
STARY STDRY
R/W
22
R
0
0
6
-
R/W
21
R
0
5
0
-
FRQ
R/W
PLR
20
R
0
4
0
-
R/W
PRR
FRQ
19
R
0
3
-
0
18
R
R
0
2
0
-
-
17
R
R
0
1
-
0
-
16
R
R
0
0
0
-
-
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