D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 1410
D6417760BP200ADV
Manufacturer Part Number
D6417760BP200ADV
Description
IC SUPER H MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D6417760BP200ADV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417760BP200ADV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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F.2
(1) Turn off the power supply of I/O and CPG to the same timing as the power supply VDDQ.
(2) There is no timing regulation of a signal line (RESET and MRESET).
(3) The input level to the pin must be lowered in compliance with the I/O, RTC, CPG power
(4) It recommends that turning off the I/O, CPG power supply voltage (VDDQ) after turning off
(5) In addition to the above (1), (2), (3), (4), and following (i), (ii), follow “F.3, The Ratings for
F.3
The LSI may be damaged when not satisfying the conditions of (1), (2), (3), and (4) below.
(1) VDDQ = VDD-CPG = AVCC–ADC
(2) VDD = VDD–PLL1 = VDD–PLL2 = VDD–PLL3
(3) –0.3V < VDD < VDDQ +0.3 V.
(4) VSS = VSSQ = VSS–PLL1=VSS–PLL2 = VSS–PLL3 = VSS–CPG = AVSS–ADC = GND
Rev. 2.00 Feb. 12, 2010 Page 1326 of 1330
REJ09B0554-0200
supply voltage.
the internal power supply voltage (VDD).
Power-on and Power-off”.
(i) In the case of this LSI simple substance, the power supply sequence of a power supply to
(ii) When this LSI is connected with other elements on the mounting board, please keep that
–0.3 V < VDD–PLL1 < VDDQ +0.3 V.
–0.3 V < VDD–PLL2 < VDDQ +0.3 V.
–0.3 V < VDD–PLL3 < VDDQ +0.3 V.
[0V].
VDDQ and VDD does not have time restrictions. Refer to figure F.1. In addition, it
recommends performing a power off at the shortest possible time.
–0.3 V < Vin < VDDQ +0.3 V.
Moreover, as shown in figure F.2, power down time (tpwd) until it goes down from an
operation voltage value {VDDQ (min), VDD (min)} to the following condition (B) is 150
ms (max).
If it is longer than that time, the LSI may be damaged.
In addition, it recommends performing a power off at the shortest possible time.
Condition (B): VDDQ < 1.0 V and VDD < 0.5 V
Power-off Procedure
The Ratings for Power-on and Power-off
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