D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 255
D6417760BP200ADV
Manufacturer Part Number
D6417760BP200ADV
Description
IC SUPER H MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D6417760BP200ADV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417760BP200ADV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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The following three kinds of operation can be used on the OC address array:
1. OC address array read
2. OC address array write (non-associative)
3. OC address array write (associative)
The tag, U bit, and V bit are read into the data field from the OC entry corresponding to the
entry set in the address field. In a read, associative operation is not performed regardless of
whether the association bit specified in the address field is 1 or 0.
The tag, U bit, and V bit specified in the data field are written to the OC entry corresponding to
the entry set in the address field. The A bit in the address field should be cleared to 0.
When a write is performed to a cache line for which the U bit and V bit are both 1, after write-
back of that cache line, the tag, U bit, and V bit specified in the data field are written.
When a write is performed with the A bit in the address field set to 1, the tag stored in the entry
specified in the address field is compared with the tag specified in the data field. If the MMU
is enabled at this time, comparison is performed after the virtual address specified by data field
bits [31:10] has been translated to a physical address using the UTLB. If the addresses match
and the V bit is 1, the U bit and V bit specified in the data field are written into the OC entry.
In other cases, no operation is performed. This operation is used to invalidate a specific OC
entry. If the OC entry U bit is 1, and 0 is written to the V bit or to the U bit, write-back is
performed. If a UTLB miss occurs during address translation, or the comparison shows a
mismatch, an exception is not generated, no operation is performed, and the write is not
executed. If a data TLB multiple hit exception occurs during address translation, processing
switches to the data TLB multiple hit exception handling routine.
Address field
Data field
31
31
U
Figure 7.7 Memory-Mapped OC Address Array
V
A
1 1 1 1 0 1 0 0
: Validity bit
: Dirty bit
: Association bit
: Reserved bits (write value should be 0, and read value is undefined )
24
23
Tag
14
13
Rev. 2.00 Feb. 12, 2010 Page 171 of 1330
10 9
Entry
5 4 3 2 1 0
A
2
REJ09B0554-0200
U
1 0
V
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