D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 277
D6417760BP200ADV
Manufacturer Part Number
D6417760BP200ADV
Description
IC SUPER H MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D6417760BP200ADV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417760BP200ADV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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8.4.1
EXPEVT consists of a 12-bit exception code. The exception code set in EXPEVT is that for a
reset or general exception event. The exception code is set automatically by hardware when an
exception occurs. EXPEVT can also be modified by software.
Initial value:
Initial value:
Note: * H'000 is set in a power-on reset, and H'020 in a manual reset.
8.4.2
INTEVT consists of a 14-bit interrupt exception code. The interrupt exception code is set
automatically by hardware when an exception occurs. INTEVT can also be modified by software.
Initial value:
Initial value:
Bit
31 to 12 ⎯
11 to 0
Bit
31 to 14 ⎯
13 to 0
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
Exception Event Register (EXPEVT)
Interrupt Event Register (INTEVT)
Bit Name
Bit Name
31
15
31
15
R
R
R
R
0
0
0
0
-
-
-
-
30
14
30
14
-
R
-
R
-
R
-
R
0
0
0
0
R/W
29
13
29
13
R
R
R
0
0
0
-
-
-
-
Initial Value
All 0
*
Initial Value
All 0
⎯
R/W
28
12
28
12
R
R
R
0
0
0
-
-
-
-
R/W
R/W
27
11
27
11
R
R
0
0
-
-
-
R/W
R/W
26
10
26
10
R
R
0
0
-
-
-
R/W
R
R/W
R/W
R
R/W
R/W
R/W
25
25
R
R
-
-
-
0
9
0
9
Description
Reserved
These bits are always read as 0, and the write
value should always be 0.
12-bit exception code
Description
Reserved
These bits are always read as 0, and the write
value should always be 0.
14-bit interrupt exception code
R/W
R/W
24
24
R
R
0
8
0
8
-
-
-
R/W
R/W
23
23
R
R
0
7
0
7
-
-
-
*
Rev. 2.00 Feb. 12, 2010 Page 193 of 1330
R/W
R/W
22
22
R
R
0
6
0
6
-
-
-
R/W
R/W
21
21
R
R
0
5
0
5
-
-
-
R/W
R/W
20
20
R
R
0
4
0
4
-
-
-
R/W
R/W
19
19
R
R
0
3
0
3
-
-
-
REJ09B0554-0200
R/W
R/W
18
18
R
R
0
2
0
2
-
-
-
R/W
R/W
17
17
R
R
0
1
0
1
-
-
-
R/W
R/W
16
16
R
R
0
0
0
0
-
-
-
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