D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 279
D6417760BP200ADV
Manufacturer Part Number
D6417760BP200ADV
Description
IC SUPER H MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D6417760BP200ADV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417760BP200ADV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 279 of 1418
- Download datasheet (9Mb)
8.5
8.5.1
(1) Power-On Reset
• Sources:
• Transition address: H'A000 0000
• Transition operations:
Power_on_reset()
{
}
⎯ RESET pin low level
⎯ When the watchdog timer overflows while the WT/IT bit is set to 1 and the RSTS bit is
Exception code H'000 is set in EXPEVT, initialization of VBR and SR is performed, and a
branch is made to PC = H'A000 0000.
In the initialization processing, the VBR register is set to H'0000 0000, and in SR, the MD,
RB, and BL bits are set to 1, the FD bit is cleared to 0, and the interrupt mask level bits
(IMASK3 to IMASK0) are set to B'1111.
CPU and on-chip peripheral module initialization is performed. For details, see the register
descriptions in the relevant sections. For some CPU functions, the TRST pin and RESET pin
must be driven low. It is therefore essential to execute a power-on reset and drive the TRST
pin low when powering on.
If the RESET pin is driven high before the MRESET pin while both these pins are low, a
manual reset may occur after the power-on reset operation. The RESET pin must be driven
high at the same time as, or after, the MRESET pin.
EXPEVT = H'0000 0000;
VBR = H'0000 0000;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
SR.IMASK = B'1111;
SR.FD = 0;
Initialize_CPU();
Initialize_Module(PowerOn);
PC = H'A000 0000;
cleared to 0 in WTCSR. For details, see section 13, Watchdog timer (WDT).
Resets
Operation
Rev. 2.00 Feb. 12, 2010 Page 195 of 1330
REJ09B0554-0200
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