D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 322
D6417760BP200ADV
Manufacturer Part Number
D6417760BP200ADV
Description
IC SUPER H MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D6417760BP200ADV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417760BP200ADV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 9 Interrupt Controller (INTC)
9.4.5
Interrupt Exception Handling and Priority
Table 9.7 lists the codes for the interrupt event register (INTEVT), and the order of interrupt
priority.
Each interrupt source is assigned a unique INTEVT code. The start address of the exception
handling routine is common to each interrupt source. Therefore, to identify the interrupt source,
branching is performed at the start of the exception handling routine using the INTEVT value. For
instance, the INTEVT value is used as a branch offset .
The priority order of the peripheral modules is specified as desired by setting priority levels from
15 to 0 in IPRA to IPRD and INTPRI00 to INTPRI0C. The priority order of the peripheral
modules is set to 0 by a reset.
When the priorities for multiple interrupt sources are set to the same level and such interrupts are
generated simultaneously, they are handled according to the default priority order shown in table
9.7.
Updating of IPRA to IPRD and INTPRI00 to INTPRI0C should only be carried out when the BL
bit in SR is set to 1. To prevent erroneous interrupt acceptance, first read one of the interrupt
priority level setting registers, then clear the BL bit to 0. This will secure the necessary timing
internally.
Rev. 2.00 Feb. 12, 2010 Page 238 of 1330
REJ09B0554-0200
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