D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 508
D6417760BP200ADV
Manufacturer Part Number
D6417760BP200ADV
Description
IC SUPER H MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D6417760BP200ADV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417760BP200ADV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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11.4
When a DMA transfer request is issued, the DMAC starts the transfer according to the
predetermined channel priority order. It ends the transfer when the transfer end conditions are
satisfied. Transfers can be requested in three modes: auto-request, external request, and on-chip
peripheral module request. There are two modes for DMA transfer: single address mode and dual
address mode. Either burst mode or cycle steal mode can be selected as the bus mode.
11.4.1
After the desired transfer conditions have been set in SAR, DAR, DMATCR, CHCR, DMAOR,
DMARCR, DMARSRA, and DMARSRB, the DMAC transfers data according to the following
procedure:
1. The DMAC checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE =
2. When a transfer request is issued and transfer has been enabled, the DMAC transfers one
3. When the specified number of transfers have been completed (when the DMATCR value
4. If a DMAC address error or NMI interrupt occurs, the DMAC suspends the transfer. It also
For details of DMA transfer end and suspension, see section 11.4.6, Ending DMA Transfer.
Rev. 2.00 Feb. 12, 2010 Page 424 of 1330
REJ09B0554-0200
0).
transfer unit of data (determined by bits TS2 to TS0). In auto-request mode, the transfer begins
automatically when the DE and DME bits are set to 1. The DMATCR value is decremented by
1 for each transfer. The actual transfer flow depends on the address mode and bus mode.
reaches 0), the transfer ends normally. If the IE bit in CHCR is set to 1 at this time, the DMAC
sends a DMTE interrupt request to the CPU.
suspends the transfer when the DE bit in CHCR or the DME bit in DMAOR is cleared to 0. In
the event of an address error, the DMAC issues a forced DMAE interrupt request to the CPU.
Operation
DMA Transfer Procedure
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