D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 509
D6417760BP200ADV
Manufacturer Part Number
D6417760BP200ADV
Description
IC SUPER H MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D6417760BP200ADV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417760BP200ADV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Figure 11.3 shows a flowchart of the DMA transfer procedure.
Notes: 1.
2.
3.
4.
In auto-request mode, transfer begins when the NMIF, AE, and TE bits are all 0 and the DE
and DME bits are set to 1.
DREQ level detection (external request) in burst mode, or cycle steal mode.
DREQ edge detection (external request) in burst mode, or auto-request mode in burst mode.
An illegal address is detected by comparing bits TS2–TS0 in CHCRn with SARn and DARn.
CHCR, DMAOR, DMARCR,
DMATCR - 1 → DMATCR
DMARSRA, DMARSRB)
Transfer (1 transfer unit)
DMTE interrupt request
(SAR, DAR, DMATCR,
Illegal address check
(reflected in AE bit)
NMIF, AE, TE = 0?
AE = 1 or DE = 0 or
Update SAR, DAR
request issued?
DE, DME = 1?
DMATCR = 0?
End of transfer
Initial settings
(when IE = 1)
DME = 0?
Yes
Yes
Yes
Yes
Yes
Transfer
NMIF or
Start
*1
Figure 11.3 DMAC Transfer Flowchart
No
No
No
No
No
*4
Normal end
Rev. 2.00 Feb. 12, 2010 Page 425 of 1330
AE = 1 or DE = 0 or
Transfer suspended
DME = 0?
Yes
NMIF or
*3
transfer request mode,
DREQ detection
No
Bus mode,
method
REJ09B0554-0200
*2
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