D6417760BP200ADV Renesas Electronics America, D6417760BP200ADV Datasheet - Page 703
D6417760BP200ADV
Manufacturer Part Number
D6417760BP200ADV
Description
IC SUPER H MPU ROMLESS 256BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet
1.D6417760BP200ADV.pdf
(1418 pages)
Specifications of D6417760BP200ADV
Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
Audio Codec, CAN, EBI/EMI, FIFO, I²C, MFI, MMC, SCI, Serial Sound, SIM, SPI, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
69
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417760BP200ADV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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(5) Serial Data Reception (Synchronous Mode)
Figure 17.19 shows a sample flowchart for serial reception.
Use the following procedure for serial data reception after enabling the SCIF for reception.
When switching the operating mode from asynchronous mode to synchronous mode without
initializing the SCIF, make sure that the ORER, PER7 to PER0, and FER7 to FER0 flags are
cleared to 0.
No
No
Read ORER flag in SCLSR
Clear RE bit in SCSCR to 0
Read RDF flag in SCFSR
SCFRDR, and clear RDF
Figure 17.19 Sample Serial Reception Flowchart (1)
Read receive data in
flag in SCFSR to 0
All data received?
Start of reception
End of reception
Initialization
ORER = 1?
RDF = 1?
No
Yes
Yes
Error handling
[1]
[3]
[4]
Yes
[2]
[1] SCIF initialization:
[2] Receive error handling:
[3] SCIF status check and receive data
[4] Serial reception continuation
Flowchart in figure 17.16.
identify any error, perform the
appropriate error handling, then clear
the ORER flag to 0.
Transmission/reception cannot be
resumed while the ORER flag is set
to 1.
read:
1, then read the receive data in
SCFRDR, and clear the RDF flag to
0. The transition of the RDF flag from
0 to 1 can also be identified by an
RXI interrupt.
procedure:
least the receive trigger set number
of receive data bytes from SCFRDR,
read 1 from the RDF flag, then clear
the RDF flag to 0. The number of
receive data bytes in SCFRDR can
be ascertained by reading SCRFDR.
See Sample SCIF Initialization
Read the ORER flag in SCLSR to
Read SCFSR and check that RDF =
To continue serial reception, read at
Rev. 2.00 Feb. 12, 2010 Page 619 of 1330
REJ09B0554-0200
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