MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 1102

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

MPC562/MPC564 Compression Features
A.2.14
The MPC562/MPC564 allows the option to switch between compressed and non-compressed code on the
fly. There are two ways to switch between the modes, as shown in
Definition for Exception
A.2.14.1
The MPC562/MPC564 can wake up upon reset with all the exception handlers defined to be compressed
(or not), so when any exception occurs or completes, the hardware switches to the appropriate mode
without software intervention.
A.2.14.2
If the compression mode is enabled on the MPC562/MPC564, the software can switch between
compressed and non-compressed code by setting (or clearing) the compression mode bit in the RCPU
MSR register. This is done by setting/clearing bit 29 in the RCPU SRR1 register (SRR1 gets loaded into
the MSR register when the rfi instruction is executed. Bit 29 is the DCMPEN bit of the MSR). The next
step is to load SRR0 with a target address in compressed/non-compressed format and then executing an rfi
instruction. Following is a suggested routine to execute the switch in both directions (must be run in
supervisor mode when RCPU MSR[PR] bit is cleared):
A.3
A.3.1
The MPC562/MPC564 provides two instruction fetch modes: decompression off and decompression on.
The operational modes are defined by RCPU MSR[DCMPEN] bit. If the bit is set, the mode is
decompression on. Otherwise, it is in decompression off.
A-14
# R30 contains destination address in appropriate format
.set turn_on_compression_bit_mask, 4
.set turn_off_compression_bit_mask, 0xfffb
mfmsr
# to go to compressed code
ori
# or alternative to go to uncompressed code:
andi.
mtspr
mtspr
mtspr
rfi
Operation Modes
Compression/Non-Compression Mode Switch
Instruction Fetch
Compression Definition for Exception Handlers
Running Mixed Code
When BBCMCR[EN_COMP] (bit 21) is set, modification of
MSR[DCMPEN] (bit 29) by mtmsr instruction is strictly forbidden. It may
cause the machine to hang until reset.
r31
r31,r31,turn_on_compression_bit_mask
r31,r31,turn_off_compression_bit_mask
NRI,r0 # Disable external interrupts
SRR1,r31
SRR0,r30 # destination address load
# branch and modify MSR
Handlers,” and
MPC561/MPC563 Reference Manual, Rev. 1.2
Section A.2.14.2, “Running Mixed
NOTE
Section A.2.14.1, “Compression
Code.”
Freescale Semiconductor