MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 153

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Table 3-2
Configuration and
Buffer Controller 2
Freescale Semiconductor
lists the MPC561/MPC563 supervisor-level registers; refer also to
Protection,”
Module,” for more information.
SPR Number
(Decimal)
272
273
274
275
284
285
18
19
22
26
27
80
81
82
Chapter 11, “L-Bus to U-Bus Interface
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 3-2. Supervisor-Level SPRs
DAE/Source Instruction Service Register (DSISR)
See
Register
Data Address Register (DAR)
See
descriptions.
Decrementer Register (DEC)
See
descriptions.
Save and Restore Register 0 (SRR0)
See
Register 0
Save and Restore Register 1 (SRR1)
See
Register 1
External Interrupt Enable (EIE)
See
Special-Purpose
External Interrupt Disable (EID)
See
Special-Purpose
Non-Recoverable Interrupt (NRI)
See
Special-Purpose
SPR General 0 (SPRG0)
See
for bit descriptions.
SPR General 1 (SPRG1)
See
for bit descriptions.
SPR General 2 (SPRG2)
See
for bit descriptions.
SPR General 3 (SPRG3)
See
for bit descriptions.
Time Base Lower – Write (TBL)
See
Time Base Upper – Write (TBU)
See
Section 3.9.2, “DAE/Source Instruction Service
Section 3.9.3, “Data Address Register
Section 6.1.6, “Decrementer
Section 3.9.6, “Machine Status Save/Restore
Section 3.9.7, “Machine Status Save/Restore
Section 3.9.10.1, “EIE, EID, and NRI
Section 3.9.10.1, “EIE, EID, and NRI
Section 3.9.10.1, “EIE, EID, and NRI
Section 3.9.8, “General SPRs
Section 3.9.8, “General SPRs
Section 3.9.8, “General SPRs
Section 3.9.8, “General SPRs
Section 6.1.7, “Time Base
Section 6.1.7, “Time Base
(DSISR),” for bit descriptions.
(SRR0),” for bit descriptions.
(SRR1),” for bit descriptions.
Special-Purpose Register
Registers.”
Registers.”
Registers.”
1
1
1
(TB).”
(TB).”
1
1
(DEC).” for bit
(SPRG0–SPRG3),”
(SPRG0–SPRG3),”
(SPRG0–SPRG3),”
(SPRG0–SPRG3),”
(L2U),” and
(DAR),” for bit
Chapter 6, “System
Chapter 4, “Burst
Central Processing Unit
3-9