MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 209

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

4.1.2
4.1.3
The following are instruction code decompression unit key features of the MPC562/MPC564. See
Appendix A, “MPC562/MPC564 Compression
Freescale Semiconductor
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Implements a parked master on the U-bus, resulting in zero clock delays for RCPU fetch accesses
to the U-bus
Fully utilizes the U-bus pipeline for fetch accesses
Avoids undesirable delays through a tight interface with the L2U module (fully utilizing U-bus
bandwidth and back-to-back accesses)
Supports program trace and show cycles
Supports a special attribute for debug port fetch accesses.
There are four regions in which the base address and size can be programmed.
Available region sizes include 2 Kbytes, 8 Kbytes, 16 Kbytes, 32 Kbytes, 64 Kbytes, 128 Kbytes,
256 Kbytes, 512 Kbytes, 1 Mbyte, 2 Mbytes, 4 Mbytes, 8 Mbytes, 16 Mbytes....4 Gbytes.
Overlap between regions is allowed.
Each of the four regions supports the following attributes:
— User/supervisor
— Guard attribute (causes an interrupt in case of speculative fetch attempt)
— Compressed/non-compressed (MPC562/MPC564 only)
— Regions are enabled or disabled in software.
Global region entry declares the default access attributes for all memory areas not covered by the
four regions:
The RCPU gets the instruction storage protection exception generated upon
— An access violation of protection attributes
— A fetch from a guarded region.
The RCPU MSR[IR] bit controls IMPU protection.
Programming is performed by using the RCPU mtspr/mfspr instructions to/from implementation
specific special-purpose registers.
The IMPU supplies relocation addresses of all the exceptions within the internal memory space.
The IMPU implements external interrupt vector splitting to reduce the external interrupt latency.
There is a special reset exception vector for decompression on mode (MPC562/MPC564 only).
Instruction code on-line decompression based on “instruction classes” algorithm.
No need for address translation between compressed and non-compressed address spaces — ICDU
provides “next instruction address” to the RCPU
In most cases, instruction decompression takes one clock
Code decompression is pipelined:
IMPU Key Features
ICDU Key Features
MPC561/MPC563 Reference Manual, Rev. 1.2
Features” for more information.
Burst Buffer Controller 2 Module
4-3