MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 24

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

17.10.3.10
17.10.4
17.10.5
17.10.6
17.10.6.1
17.10.6.2
17.10.6.3
17.10.6.4
17.10.6.5
17.11
17.11.1
17.11.2
17.11.3
17.11.3.1
17.11.3.2
17.11.4
17.11.5
17.11.6
17.11.7
17.11.8
17.11.8.1
17.11.8.2
17.12
17.12.1
17.12.2
17.12.3
17.12.3.1
17.12.3.2
17.12.3.3
17.12.4
17.12.4.1
17.12.4.2
17.12.4.3
17.12.5
17.12.6
17.12.6.1
17.12.6.2
17.13
17.13.1
17.13.2
17.13.3
Freescale Semiconductor
Paragraph
Number
MIOS14 16-bit Parallel Port I/O Submodule (MPIOSM) .......................................... 17-60
MIOS14 Interrupts ...................................................................................................... 17-63
MIOS14 Function Examples ...................................................................................... 17-70
Modular Input/Output Bus (MIOS14) Interface ..................................................... 17-54
Effect of RESET on MPWMSM ............................................................................ 17-54
MPWMSM Registers .............................................................................................. 17-55
MPIOSM Features .................................................................................................. 17-61
MPIOSM Signal Functions ..................................................................................... 17-61
MPIOSM Description ............................................................................................. 17-61
Modular I/O Bus (MIOB) Interface ........................................................................ 17-62
Effect of RESET on MPIOSM ............................................................................... 17-62
MPIOSM Testing .................................................................................................... 17-62
MPIOSM Registers ................................................................................................. 17-62
MPIOSM Register Organization ............................................................................ 17-62
MIOS14 Interrupt Structure .................................................................................... 17-63
MIOS14 Interrupt Request Submodule (MIRSM) ................................................. 17-64
MIRSM0 Interrupt Registers .................................................................................. 17-65
MIRSM1 Interrupt Registers .................................................................................. 17-67
Interrupt Control Section (ICS) .............................................................................. 17-69
MBISM Interrupt Registers .................................................................................... 17-69
MIOS14 Input Double Edge Pulse Width Measurement ........................................ 17-70
MIOS14 Input Double Edge Period Measurement ................................................. 17-71
MIOS14 Double Edge Single Output Pulse Generation ......................................... 17-72
MPWMSM Data Coherency ............................................................................... 17-54
MPWMSM Registers Organization .................................................................... 17-55
MPWMSM Period Register (MPWMPERR) ..................................................... 17-57
MPWMSM Pulse Width Register (MPWMPULR) ........................................... 17-57
MPWMSM Counter Register (MPWMCNTR) .................................................. 17-58
MPWMSM Status/Control Register (MPWMSCR) ........................................... 17-58
MPIOSM Port Function ...................................................................................... 17-61
Non-Bonded MPIOSM Pads .............................................................................. 17-61
MPIOSM Data Register (MPIOSMDR) ............................................................. 17-62
MPIOSM Data Direction Register (MPIOSMDDR) .......................................... 17-63
Interrupt Status Register (MIOS14SR0) ............................................................. 17-65
Interrupt Enable Register (MIOS14ER0) ........................................................... 17-66
Interrupt Request Pending Register (MIOS14RPR0) ......................................... 17-66
Interrupt Status Register (MIOS14SR1) ............................................................. 17-67
Interrupt Enable Register (MIOS14ER1) ........................................................... 17-68
Interrupt Request Pending Register (MIOS14RPR1) ......................................... 17-68
MIOS14 Interrupt Level Register 0 (MIOS14LVL0) ........................................ 17-69
MIOS14 Interrupt Level Register 1 (MIOS14LVL1) ........................................ 17-70
MPC561/MPC563 Reference Manual, Rev. 1.2
Contents
Title
Number
Page
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