MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 244

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

System Configuration and Protection
6.1.1.1
Some of the functions defined in the various sections of the USIU (external bus interface, memory
controller, and general-purpose I/O) share pins.
multiplexed pins are assigned.
6.1.1.2
Two bits in the SIUMCR control USIU bus arbitration. The external arbitration (EARB) bit determines
whether arbitration is performed internally or externally. If EARB is cleared (internal arbitration), the
external arbitration request priority (EARP) bit determines the priority of an external master’s arbitration
request. The operation of the internal arbiter is described in
6.1.2
External master modes are special modes of operation that allow an alternative master on the external bus
to access the internal modules for debugging and backup purposes. They provide access to the internal
buses (U-bus and L-bus) and to the intermodule bus (IMB3).
There are two external master modes:
6-4
.
•
IRQ0 / SGPIOC0 / MDO4
IRQ1 / RSV / SGPIOC1
IRQ2 / CR / SGPIOC2 / MTS
IRQ3 / KR / RETRY / SGPIOC3
IRQ4 / AT2 / SGPIOC4
IRQ5 / SGPIOC5 / MODCK1
IRQ6 / MODCK2
IRQ7 / MODCK3
SGPIOC6 / FRZ / PTR
SGPIOC7 / IRQOUT / LWP0
BG / VF0 / LWP1
BR / VF1 / IWP2
BB / VF2 / IWP3
IWP[0:1] / VFLS[0:1]
BI / STS
WE[0:3] / BE[0:3] / AT[0:3]
TDI/DSDI / MDI0
TCK / DSCK / MCKI
TDO / DSDO / MDO0
DATA[0:31] / SGPIOD[0:31]
ADDR[8:31] / SGPIOA[8:31]
RSTCONF /TEXP
Peripheral mode (enabled by setting PRPM in the external master control (EMCR) register) uses a
special slave mechanism that shuts down the RCPU and an alternative master on the external bus
can perform accesses to any internal bus slave.
External Master Modes
USIU Pin Multiplexing
Arbitration Support
Pin Name
Table 6-1. USIU Pin Multiplexing Control
MPC561/MPC563 Reference Manual, Rev. 1.2
Note:MDIO, MCKI, and MDO0 are controlled by READI enable.
Programmed in SIUMCR and Hard Reset Configuration
Table 6-1
Note:MDO4 is controlled by READI enable.
Otherwise: Programmed in SIUMCR
Otherwise: Programmed in SIUMCR
At Power-On Reset: MODCK[1:3]
At Power-On Reset: RSTCONF
Multiplexing Controlled by:
Programmed in SIUMCR
summarizes how the pin functions of these
Section 9.5.7.4, “Internal Bus
Freescale Semiconductor
Arbiter.”