MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 245

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Both modes can be enabled and disabled by software. In addition, peripheral mode can be selected from
reset.
The internal bus is not capable of providing priority between internal RCPU accesses and external master
accesses. If the bandwidth of external master accesses is large, it is recommended that the system force
gaps between external master accesses in order to avoid suspension of internal RCPU activity.
The MPC561/MPC563 does not support burst accesses from an external master; only single accesses of 8,
16, or 32 bits can be performed. The MPC561/MPC563 asserts burst inhibit (BI) on any attempt to initiate
a burst access to internal memory.
The MPC561/MPC563 provides memory controller services for external master accesses (single and
burst) to external memories. See
6.1.2.1
The external master modes are controlled by the EMCR register, which contains the internal bus attributes.
The default attributes in the EMCR allow an external master to configure the EMCR with the required
attributes and access internal registers. The external master must be granted external bus ownership in
order to initiate the external master access. The SIU compares the address on the external bus to the
allocated internal address space. If the address is within the internal space, the access is performed with
the internal bus. The internal address space is determined according to IMMR[ISB] (see
“Internal Memory Map Register
TA, TEA, or RETRY signal on the external bus.
A deadlock situation might occur if an internal-to-external access is attempted on the internal bus while an
external master access is initiated on the external bus. In this case, the SIU will assert RETRY on the
external bus in order to relinquish and retry the external access until the internal access is completed. The
internal bus will deny other internal accesses for the next eight clocks in order to complete the pending
accesses and prevent additional internal accesses from being initiated on the internal bus. The SIU will
also mask internal accesses to support consecutive external accesses if the delay between the external
accesses is less than four clocks. The external master access and retry timings are described in
Section 9.5.12, “Bus Operation in External Master
The external master may access the internal MPC561/MPC563 special registers that are located outside
the RCPU. To access one of these special purpose registers (see
Registers”), EMCR[CONT] must be set and EMCR[SUPU] must be cleared. The external master can then
access the special register when it is provided the address according to the MPC561/MPC563 address map.
Only the first external master access that follows EMCR setting will be assigned to the special register
map; any subsequent accesses will be directed to the normal address map. This is done in order to enable
access to the EMCR again after the required MPC561/MPC563 special register access.
Peripheral mode does not require external bus arbitration between the external master and the internal
RCPU, since the internal RCPU is disabled. The BR and BB signals should be connected to ground, and
the internal bus arbitration should be selected in order to prevent the “slave” MPC561/MPC563 from
Freescale Semiconductor
Slave mode (enabled by setting EMCR[SLVM] and clearing EMCR[PRPM]) enables an external
master to access any internal bus slave while the RCPU is fully operational.
Operation in External Master Modes
MPC561/MPC563 Reference Manual, Rev. 1.2
(IMMR),” for details). The external master access is terminated by the
Chapter 10, “Memory
Modes.”
Controller,” for details.
Section 5.1.1, “USIU Special-Purpose
System Configuration and Protection
Section 6.2.2.1.2,
6-5

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