MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 290

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Reset
If limp mode is enabled, the internal PLL is not required to be locked before the chip exits power-on reset.
The internal MODCK[1:3] values are sampled at the rising edge of PORESET. After exiting the power-on
reset state, the MPC561/MPC563 continues to drive the HRESET and SRESET pins for 512 system clock
cycles. When the timer expires (after 512 cycles), the configuration is sampled from data bus pins, if
required (see
HRESET and SRESET pins.
The PORESET pin has a glitch detector to ensure that low spikes of less than 20 ns are rejected. The
internal PORESET signal asserts only if the PORESET pin asserts for more than 100 ns.
7.1.2
HRESET (hard reset) is an active low, bidirectional I/O pin. The MPC561/MPC563 can detect an external
assertion of HRESET only if it occurs while the MPC561/MPC563 is not asserting HRESET.
When the MPC561/MPC563 detects assertion of the external HRESET pin or a cause to assert the internal
HRESET line is detected, the chip starts to drive the HRESET and SRESET for 512 cycles. When the timer
expires (after 512 cycles) the configuration is sampled from data pins (refer to
Configuration”) and the chip stops driving the HRESET and SRESET pins. An external pull-up resistor
should drive the HRESET and SRESET pins high. After detecting the negation of HRESET or SRESET,
the MPC561/MPC563 waits 16 clock cycles before testing the presence of an external hard or soft reset.
The HRESET pin has a glitch detector to ensure that low spikes of less than 20 ns are rejected. The internal
HRESET will be asserted only if HRESET is asserted for more than 100 ns.
The HRESET is an open collector type pin.
7.1.3
SRESET (soft reset) is an active low, bidirectional I/O pin. The MPC561/MPC563 can only detect an
external assertion of SRESET if it occurs while the MPC561/MPC563 is not asserting SRESET.
When the MPC561/MPC563 detects the assertion of external SRESET or a cause to assert the internal
SRESET line, the chip starts to drive the SRESET for 512 cycles. When the timer expires (after 512 cycles)
the debug port configuration is sampled from the DSDI and DSCK pins and the chip stops driving the
SRESET pin. An external pull-up resistor should drive the SRESET pin high. After the MPC561/MPC563
detects the negation of SRESET, it waits 16 clock cycles before testing the presence of an external soft
reset.
The SRESET is an open collector type pin.
7.1.4
devices use the MPC561/MPC563 input clock. Erroneous operation could also occur if devices with a PLL
7-2
If the PLL detects a loss of lock, erroneous external bus operation will occur if synchronous external
The Internal PLL enters the lock state and the system clock is active.
The PORESET pin is negated.
Hard Reset
Soft Reset
Loss of PLL Lock
Section 7.5.1, “Hard Reset
MPC561/MPC563 Reference Manual, Rev. 1.2
Configuration”) and the MPC561/MPC563 stops driving the
Section 7.5.1, “Hard Reset
Freescale Semiconductor

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