MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 357

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Refer to
Controller Option Registers
configuration bits.
9.5.4
The MPC561/MPC563 uses non-wrapping burst transfers to access operands of up to 32 bytes (eight
words). A non-wrapping burst access stops accessing the external device when the word address is modulo
four/eight. Burst configuration is determined by the value of BURST_EN in the SIUMCR register. See
Chapter 5, “Unified System Interface Unit (USIU)
begins the access by supplying a starting address that points to one of the words in the array and requires
the memory to sequentially drive or sample each word on the data bus. The selected slave device must
internally increment ADDR28 and ADDR29 (and ADDR30 in the case of a 16-bit port slave device, and
also ADDR31 in the case of an 8-bit port slave device) of the supplied address for each transfer, causing
the address to reach a four/eight word boundary, and then stop. The address and transfer attributes supplied
by the MPC561/MPC563 remain stable during the transfers. The selected device terminates each transfer
by driving or sampling the word on the data bus and asserting TA.
Freescale Semiconductor
CLKOUT
ADDR[8:31]
TS
RD/WR
TA
OE
Data
Figure 9-11. Read Followed by Write when Pre-Discharge Mode is Enabled, and EHTR is Set
Section 2.4, “Pad Module Configuration Register
Burst Transfer
Read Data
Read Cycle
(OR0–OR3),” for more information on PREDIS_EN, and EHTR
EHTR provides 1 clock
gap to three-state data bus
MPC561/MPC563 Reference Manual, Rev. 1.2
Overview” for further details. The MPC561/MPC563
Pre-discharge
to low voltage
(PDMCR2),” and
Write Cycle
Section 10.9.4, “Memory
Write Data
External Bus Interface
9-17

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