MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 546

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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QADC64E Enhanced Mode Operation
Accesses to supervisor-only data space is permitted only when the bus master is operating in supervisor
access mode. Assignable data space can be either restricted to supervisor-only access or unrestricted to
both supervisor and user data space addresses. See
Space.”
14.2.3
The QADC64E modules can be configured to operate in Legacy or Enhanced mode. Legacy mode is the
default state out of reset. The QADC64E modules are configured for Enhanced mode by a series of writes
14-4
1
0x30 4C14-
0x30 4E00-
0x30 4E80-
0x30 4F00-
0x30 4C0A EMUX
0x30 4C0C
0x30 4C0E
0x30 4DFF
0x30 4C00
0x30 4C02
0x30 4C04
0x30 4C06
0x30 4C08
0x30 4C10
0x30 4C12
0x30 4E7F
0x30 4EFF
0x30 4F7F
0x30 4FFF
0x30 4F80
Address
Registers are accessible only as supervisor data space
Legacy and Enhanced Modes of Operation
STOP FRZ
SIGN
CIE1
CIE2
CF1
MSB
0
TEST MODE
PF1
PIE
PIE
1
2
1
IRL1
SSE1
SSE2
CF2
0000 00
2
UNSIGNED LEFT JUSTIFIED
PF2 TOR
PORTQA
TR
DDRQA
MPC561/MPC563 Reference Manual, Rev. 1.2
G
3
Table 14-2. QADC64E_B Address Map
SIGNED LEFT JUSTIFIED
1
CWPQ1
4
TOR2
MQ1
MQ2
5
Reserved
LOC
K
P
6
Section 14.3.1.4, “Supervisor/Unrestricted Address
IRL2
FLI
RE
P
F
7
UNSIGNED RIGHT JUSTIFIED
QS
RESU
SUPV
IST
ME
8
9
QCLK PRESCALER
10
PORTQB
DDRQB
11
CHAN
BQ2
CWPQ2
00 0000
00 0000
12
CWP
13
Freescale Semiconductor
14
LSB
15
Reserved
Port Data
Control 0
Control 1
Control 2
Register
Direction
Interrupt
Config.
Status 0
Status 1
Module
Results
Results
Results
CCWs
Test
Port
1

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