MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 565

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Freescale Semiconductor
Bits
1
2
Name
PF1
CF2
Queue 1 Pause Flag. PF1 indicates that a queue 1 scan has reached a pause. PF1 is set
by the QADC64E when the current queue 1 CCW has the pause bit set, the selected input
channel has been converted, and the result has been stored in the result table.
Once PF1 is set, the queue enters the paused state and waits for a trigger event to allow
queue execution to continue. However, if the CCW with the pause bit set is the last CCW
in a queue, the queue execution is complete. The queue status becomes idle, not paused,
and both the pause and completion flags are set. Another exception occurs in software
controlled mode, where the PF1 can be set but queue 1 never enters the pause state since
queue 1 continues without pausing.
When PF1 is set and interrupts are enabled for the corresponding queue, the QADC64E
asserts an interrupt request at the level specified by IRL1 in the interrupt register. The
software may read PF1 during an interrupt service routine to identify the interrupt request.
The interrupt request is cleared when the software writes a zero to PF1, when the bit was
previously read as a one. Once set, only software or reset can clear PF1.
In external gated single-scan and continuous-scan mode the definition of PF1 has been
redefined. When the gate closes before the end-of-queue 1 is reached, PF1 becomes set
to indicate that an incomplete scan has occurred.In single-scan mode, setting PF1 can be
used to cause an interrupt and software can then determine if queue 1 should be enabled
again. In either external gated mode, setting PF1 indicates that the results for queue 1 have
not been collected during one scan (coherently).
NOTE: If a pause in a CCW is encountered in external gated mode for either single-scan
and continuous-scan mode, the pause flag will not set, and execution continues without
pausing. This has allowed for the added definition of PF1 in the external gated modes.
PF1 is maintained by the QADC64E regardless of whether the corresponding interrupts
are enabled. The software may poll PF1 to find out when the QADC64E has reached a
pause in scanning a queue.The software acknowledges that it has detected a pause flag
being set by writing a zero to PF1 after the bit was last read as a one.
0 = queue 1 has not reached a pause (or gate has not closed before end-of-queue in gated
1 = queue 1 has reached a pause (or gate closed before end-of-queue in gated mode)
Refer to
Queue 2 Completion Flag. CF2 indicates that a queue 2 scan has been completed. CF2 is
set by the QADC64E when the input channel sample requested by the last CCW in queue
2 is converted, and the result is stored in the result table.
The end-of-queue 2 is identified when the current CCW contains an end-of-queue code
instead of a valid channel number, or when the currently completed CCW is in the last
location of the CCW RAM.
When CF2 is set and interrupts are enabled for that queue completion flag, the QADC64E
asserts an interrupt request at the level specified by IRL2 in the interrupt register
(QADCINT). The software reads CF2 during an interrupt service routine to identify the
interrupt request. The interrupt request is cleared when the software writes a zero to the
CF2 bit, when the bit was previously read as a one. Once set, only software or reset can
clear CF2.
CF2 is maintained by the QADC64E regardless of whether the corresponding interrupts
are enabled. The software polls for CF2 to see if it is set. This allows the software to
recognize that the QADC64E is finished with a queue 2 scan. The software acknowledges
that it has detected the completion flag being set by writing a zero to the completion flag
after the bit was read as a one.
mode)
Table 14-15. QASR0 Bit Descriptions (continued)
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 14-16
for a summary of pause response in all scan modes.
Description
QADC64E Enhanced Mode Operation
14-23