MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 576

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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QADC64E Enhanced Mode Operation
The channel field is programmed for channel 63 to indicate the end of the queue. Channels 60 to 62 are
special internal channels. When one of the special channels is selected, the sampling amplifier is not used.
The value of V
channels, programming any input sample time other than two has no benefit except to lengthen the overall
conversion time.
14.3.10 Result Word Table
The result word table is a RAM, 64 words long and 10 bits wide. An entry is written by the QADC64E
after completing an analog conversion specified by the corresponding CCW table entry. Software can read
or write the result word table, but in normal operation, the software reads the result word table to obtain
analog conversions from the QADC64E. Unimplemented bits are read as zeros, and write operations do
not have any effect. See
While there is only one result word table, the data can be accessed in three different data formats:
14-34
Table 14-21. QADC64E_B Multiplexed Channel Assignments and Signal Designations (continued)
1
VRH/ALTREF
Port Signal
Whichever is selected in the CCW.
Right justified in the 16-bit word, with zeros in the higher order unused bits
Left justified, with the most significant bit inverted to form a sign bit, and zeros in the unused lower
order bits
Left justified, with zeros in the lower order unused bits
B_PQB4
B_PQB5
B_PQB6
B_PQB7
B_PQA0
B_PQA1
B_PQA2
B_PQA3
B_PQA4
B_PQA5
B_PQA6
B_PQA7
Name
VRL
RL
1
, V
Signal Name
RH
RESERVED
High Ref
Low Ref
Analog
, or (V
AN48
AN47
AN50
AN51
AN52
AN53
AN54
AN55
AN56
AN57
AN58
AN59
Figure 14-15
Multiplexed Input Signals
RH
- V
MPC561/MPC563 Reference Manual, Rev. 1.2
End of Queue Code
RL
Other Functions /
(VRH – VRL)/2
Descriptions
)/2 is placed directly onto the converter. Also for the internal special
for a diagram of the result word table
MA0
MA1
MA2
Signal Type
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input
Input
Channel Number in CCW CHAN
1011000 to
0110000
0110001
0110010
0110011
0110100
0110101
0110110
0110111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
1111111
Binary
Field
Freescale Semiconductor
64 to 127
Decimal
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

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