MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 602

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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QADC64E Enhanced Mode Operation
The above situations cover normal overlap conditions that arise with asynchronous trigger events on the
two queues. An additional conflict to consider is that the freeze condition can arise while the QADC64E
is actively executing CCWs. The conventional use for the freeze mode is for software/hardware
debugging. When the CPU background debug mode is enabled and a breakpoint occurs, the freeze signal
is issued, which can cause peripheral modules to stop operation. When freeze is detected, the QADC64E
completes the conversion in progress, unlike queue 1 suspending queue 2. After the freeze condition is
removed, the QADC64E continues queue execution with the next CCW in sequence.
Trigger events that occur during freeze are not captured. When a trigger event is pending for queue 2 before
freeze begins, that trigger event is remembered when the freeze is passed. Similarly, when freeze occurs
while queue 2 is suspended, after freeze, queue 2 resumes execution as soon as queue 1 is finished.
Situations 12 through 19
14-60
Q1
Q2
QS
0000
IDLE
Q2:
IDLE
T2
C1
ACTIVE
0010
(Figure 14-36
C2
Q1:
Q1:
T1
SUSPEND
T1
TOR2
MPC561/MPC563 Reference Manual, Rev. 1.2
C1
Figure 14-35. CCW Priority Situation 11
ACTIVE
Figure 14-36. CCW Freeze Situation 12
T2
C1
1010
C2
C2
to
PF1
Figure
ACT
0110
C2
PF2
PAUSE
0101
FREEZE
PAUSE
14-43) show examples of all of the freeze situations.
T2
C3
ACTIVE
0110
C4
T1
SUSPEND
TOR2
C3
T2
ACTIVE
1010
C3
C4
CF1
C4
ACT
CF1
0010
C4
CF2
RESUME=1
IDLE
Freescale Semiconductor
QADC S12
IDLE
0000
QADC S11

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