MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 671

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

where SCxBR is in the range {1, 2, 3, ..., 8191}.
The SCI receiver operates asynchronously. An internal clock is necessary to synchronize with an incoming
data stream. The SCI baud rate generator produces a receive time sampling clock with a frequency 16
times that of the SCI baud rate. The SCI determines the position of bit boundaries from transitions within
the received waveform, and adjusts sampling points to the proper positions within the bit period.
Table 15-30
clock speed is 1250 Kbaud.
15.7.7.4
The PT bit in SCCxR1 selects either even (PT = 0) or odd (PT = 1) parity. PT affects received and
transmitted data. The PE bit in SCCxR1 determines whether parity checking is enabled (PE = 1) or
disabled (PE = 0). When PE is set, the MSB of data in a frame (i.e., the bit preceding the stop bit) is used
for the parity function. For transmitted data, a parity bit is generated. For received data, the parity bit is
checked. When parity checking is enabled, the PF bit in the SCI status register (SCxSR) is set if a parity
error is detected.
Enabling parity affects the number of data bits in a frame, which can in turn affect frame size.
shows possible data and parity formats.
Freescale Semiconductor
shows possible baud rates for a 40-MHz IMB3 clock. The maximum baud rate with this IMB3
Parity Checking
1,250,000.00
Baud Rate
1
57,600.00
38,400.00
32,768.00
28,800.00
19,200.00
14,400.00
Nominal
9,600.00
4,800.00
2,400.00
1,200.00
These rates are based on a 40-MHz IMB3 clock.
600.00
300.00
Table 15-31. Effect of Parity Checking on Data Size
M
0
0
Table 15-30. Examples of SCIx Baud Rates
MPC561/MPC563 Reference Manual, Rev. 1.2
SCxBR
1,250,000.00
Baud Rate
56,818.18
37,878.79
32,894.74
29,069.77
19,230.77
14,367.81
9,615.38
4,807.69
2,399.23
1,199.62
Actual
600.09
299.98
=
------------------------------------------------------------------------
32xSCI Baud Rate Desired
PE
0
1
f SYS
8 data bits
7 data bits, 1 parity bit
Percent
Error
-1.36
-1.36
-0.22
-0.03
-0.03
-0.01
0.00
0.39
0.94
0.16
0.16
0.16
0.02
Result
1
Value of
SCxBR
1042
2083
4167
130
260
521
22
33
38
43
65
87
Queued Serial Multi-Channel Module
1
Table 15-31
15-53