MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 678

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Queued Serial Multi-Channel Module
15.8.2.1
15-60
SRESET
Bits
0:3
4
5
6
7
8
9
Field
Addr
QSCI1 Control Register (QSCI1CR)
MSB
QTPNT
QBHFI
QTHEI
QBHEI
QTHFI
Name
0
QTE
—
QTPNT
1
Queue transmit pointer. QTPNT is a 4-bit counter used to indicate the next data frame within the
transmit queue to be loaded into the SC1DR. This feature allows for ease of testability. This field
is writable in test mode only; otherwise it is read-only.
Receiver queue top-half full interrupt. When set, QTHFI enables an SCI1 interrupt whenever the
QTHF flag in QSCI1SR is set. The interrupt is blocked by negating QTHFI. This bit refers to the
queue locations SCRQ[0:7].
0 QTHF interrupt inhibited
1 Queue top-half full (QTHF) interrupt enabled
Receiver queue bottom-half full interrupt. When set, QBHFI enables an SCI1 interrupt whenever
the QBHF flag in QSCI1SR is set. The interrupt is blocked by negating QBHFI. This bit refers to
the queue locations SCRQ[8:15].
0 QBHF interrupt inhibited
1 Queue bottom-half full (QBHF) interrupt enabled
Transmitter queue top-half empty interrupt. When set, QTHEI enables an SCI1 interrupt
whenever the QTHE flag in QSCI1SR is set. The interrupt is blocked by negating QTHEI. This bit
refers to the queue locations SCTQ[0:7].
0 QTHE interrupt inhibited
1 Queue top-half empty (QTHE) interrupt enabled
Transmitter queue bottom-half empty interrupt. When set, QBHEI enables an SCI1 interrupt
whenever the QBHE flag in QSCI1SR is set. The interrupt is blocked by negating QBHEI. This
bit refers to the queue locations SCTQ[8:15].
0 QBHE interrupt inhibited
1 Queue bottom-half empty (QBHE) interrupt enabled
Reserved
Queue transmit enable. When set, the transmit queue is enabled and the TDRE bit should be
ignored by software. The TC bit is redefined to indicate when the entire queue is finished
transmitting. When clear, the SCI1 functions as described in the previous sections and the bits
related to the queue (Section 5.5 and its subsections) should be ignored by software with the
exception of QTE.
0 Transmit queue is disabled
1 Transmit queue is enabled
2
Figure 15-31. QSCI1 Control Register (QSCI1CR)
3
QTHFI QBHFI QTHEI QBHEI
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 15-32. QSCI1CR Bit Descriptions
4
5
0000_0000_0000_0000
6
0x30 5028
7
Description
—
8
QTE
9
QRE QTWE
10
11
Freescale Semiconductor
12
13
QTSZ
14
LSB
15