MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 761

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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The 16-bit counter bus selector is common to all input and output functions; it connects the MDASM to
one of the four 16-bit counter buses available to that submodule instance and is controlled in software by
the 16-bit counter bus selector bits BSL0 and BSL1 in the MDASMSCR register.
17.9.3
The mode of operation of the MDASM is determined by the mode select bits MODE[0:3] in the
MDASMSCR register (see
To avoid spurious interrupts, and to make sure that the FLAG line is activated according to the newly
selected mode, the following sequence of operations should be adopted when changing mode:
17.9.3.1
The disable mode is selected by setting MODE[0:3] to 0b0000.
In this mode, all input capture and output compare functions of the MDASM are disabled and the FLAG
line is maintained inactive, but the input port signal function remains available. The associated signal
becomes a high impedance input and the input level on this signal is reflected by the state of the PIN bit
in the MDASMSCR register. All control bits remain accessible, allowing the software to prepare for future
Freescale Semiconductor
MODE[0:3]
1. Disable MDASM interrupts (by resetting the enable bit in the relevant MIRSM)
2. Change mode (via disable mode)
3. Reset the corresponding FLAG bit in the relevant MIRSM
4. Re-enable MDASM interrupts (if desired)
0000
0001
0010
0011
0100
0101
1xxx
MDASM Modes of Operation
OPWM
OCAB
IPWM
Disable (DIS) Mode
Mode
OCB
IPM
DIS
IC
When changing between output modes, it is not necessary to follow this
procedure, as in these modes the FLAG bit merely indicates to the software
that the compare value can be updated. However changing modes without
passing via the disable mode does not guarantee the subsequent
functionality.
Disabled — Input signal is high impedance; PIN gives state of the input signal.
Input pulse width measurement — Capture on the leading edge and the trailing edge of an input pulse.
Input period measurement — Capture two consecutive rising/falling edges.
Input capture — Capture when the designated edge is detected.
Output compare, flag line activated on B compare — Generate leading and trailing edges of an output
pulse.
Output compare, flag line activated on A and B compare — Generate leading and trailing edges of an
output pulse.
Output pulse width modulation — Generate continuous PWM output with 7, 9, 11, 12, 13, 14, 15 or 16
bits of resolution.
Table
Table 17-16. MDASM Modes of Operation
MPC561/MPC563 Reference Manual, Rev. 1.2
17-16).
NOTE
Description of Mode
Modular Input/Output Subsystem (MIOS14)
17-29

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