MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 768

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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Modular Input/Output Subsystem (MIOS14)
17.9.3.5.3
The output port bit operation is selected by leaving both channels disabled, (i.e., by writing to neither
register A nor B). The EDPOL bit alone controls the output value. The same result can be achieved by
keeping EDPOL at zero and using the FORCA and FORCB bits to obtain the desired output level.
17.9.3.6
OPWM mode is selected by setting MODE[0:3] to 1xxx. The MODE[1:3] bits allow some of the
comparator bits to be masked.
This mode allows pulse width modulated output waveforms to be generated, with eight selectable
frequencies. Frequencies are only relevant as such if the counter bus is driven by a counter as a time
reference. Both channels (A and B) are used to generate one PWM output signal on the MDASM signal.
Channel B is accessed via register B1. Register B2 is not accessible. Channels A and B define respectively
the leading and trailing edges of the PWM output pulse. The value in register B1 is transferred to register
B2 each time a match occurs on either channel A or B.
The value loaded in register A is compared with the value on the 16-bit counter bus each time the counter
bus is updated. When a match on A occurs, the FLAG line is activated and the output flip-flop is set. The
value loaded in register B2 is compared with the value on the 16-bit counter bus each time the counter bus
is updated. When a match occurs on B, the output flip-flop is reset.
17-36
Output signal
Mode selection; MODE0 = 1
Internal Register, not accessible to software
Register B1
Register B2
Register A
FLAG bit
Counter Bus
16-bit
Output Pulse Width Modulation (OPWM) Mode
Output Port Bit Operation
A FORCA or FORCB does not cause a transfer from B1 to B2.
Write to A
0x1000
0xxxxx
0xxxxx
0x0500
Figure 17-20. Single Shot Output Transition Example
F LAG reset
by software
MPC561/MPC563 Reference Manual, Rev. 1.2
0x1000
0x1000
0xxxxx
0xxxxx
A Event
Reoccurences of the timer count do
not trigger a response unless registers
A or B have been written again.
0x1100
0x1000
0xxxxx
0xxxxx
NOTE
Write to B
0x1000
0x1000
0xxxxx
0x1100
B Event
0x1000
0xxxxx
0x1100
0x1100
FLAG reset
by software
Freescale Semiconductor
0x1000
0xxxxx
0x1000
0x1100

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