MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 91

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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1.3.3.3
1.3.3.4
Freescale Semiconductor
12 dedicated PWM sub-modules (PWMSM)
One MIOS14 16-bit parallel port I/O sub-modules (MPIOSM)
Two queued analog-to-digital converter modules (QADC64E_A, QADC64E_B) providing a total
of 32 analog channels
16 analog input channels on each QADC64E module using internal multiplexing
Directly supports up to four external multiplexers
Up to 41 total input channels on the two QADC64E modules with external multiplexing
Software configurable to operate in enhanced or legacy (MPC555 compatible) mode
Unused analog channels can be used as digital input/output signals
— GPIO on all channels in enhanced mode
10-bit A/D converter with internal sample/hold
Minimum conversion time of 7 µs (with typical QCLK frequency, 2 MHz) and +/- 2 bits accuracy
Two conversion command queues of variable length
Automated queue modes initiated by:
— External edge trigger
— Software command
— Periodic/interval timer within the QADC64E module, that can be assigned to both queue 1 and
— External gated trigger (queue 1 only)
64 result registers
— Output data is right- or left-justified, signed or unsigned.
Alternate reference input (ALTREF), with control in the conversion command word (CCW)
Three TouCAN modules (TouCAN_A, TouCAN_B, TouCAN_C)
Each TouCAN provides the following features:
— 16 message buffers, programmable I/O modes
— Maskable interrupts
— Independent of the transmission medium (external transceiver is assumed)
— Open network architecture, multi-master concept
— High immunity to EMI
— Short latency time for high-priority messages
— Low-power sleep mode, with programmable wake-up on bus activity
— TouCAN_C pins are shared with MIOS14 GPIO or QSMCM
2
Two Enhanced Queued Analog-to-Digital Converter Modules
(QADC64E)
Three CAN 2.0B Controller (TouCAN) Modules
MPC561/MPC563 Reference Manual, Rev. 1.2
Overview
1-7

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