MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 935

IC MPU 32BIT 56MHZ PPC 388-PBGA

MPC562MZP56

Manufacturer Part Number
MPC562MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet

Specifications of MPC562MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No

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The development port provides a full duplex serial interface for communications between the internal
development support logic of the CPU and an external development tool. The development port can
operate in two working modes: the trap enable mode and the debug mode.
The trap enable mode is used in order to shift into the CPU internal development support logic the
following control signals:
In debug mode the development port controls also the debug mode features of the CPU. For more
information
23.3.1
The debug mode of the CPU provides the development system with the following basic functions:
Freescale Semiconductor
1. Instruction trap enable bits, used for on the fly programming of the instruction breakpoint
2. Load/store trap enable bits, used for on the fly programming of the load/store breakpoint
3. Non-maskable breakpoint, used to assert the non-maskable external breakpoint
4. Maskable breakpoint, used to assert the maskable external breakpoint
5. VSYNC, used to assert and negate VSYNC
DSCK
DSDI
Debug Mode Support
Section 23.4, “Development
Figure 23-5. Functional Diagram of MPC561/MPC563 Debug Mode Support
BKPT, TE,
VSYNC
CPU Core
ECR
DER
9
MPC561/MPC563 Reference Manual, Rev. 1.2
Port.”
TECR
Development Port
Development Port
Shift Register
Control Logic
32
35
DPDR
DPIR
32
Internal
Bus
Development
Port
SIU/
EBI
Logic
Support
Development Support
EXT
BUS
VFLS,
DSDO
FRZ
23-21

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