MPC562MZP56 Freescale Semiconductor, MPC562MZP56 Datasheet - Page 967

• Manufacturer Part Number: MPC562MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC562MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

23.6.12 Breakpoint Address Register (BAR)
23.6.13 Development Port Data Register (DPDR)
This 32-bit special purpose register physically resides in the development port logic. It is used for data
interchange between the core and the development system. An access to this register is initiated using
mtspr and mfspr (SPR 630) and implemented using a special bus cycle on the internal bus.
Freescale Semiconductor
Reset
Field
Addr
SRESET
Serialize
Control
(SER)
Field
Addr
Bits
0:31
MSB
1
1
1
1
0
MSB
1
0
Instruction
2
(ISCTL)
1
Fetch
00
01
10
11
BARV[0:31]
Mnemonic
3
2
4
3
5
4
Illegal. This mode should not be selected.
RCPU is not serialized (normal mode) and show cycles will be performed for all changes in
the program flow
RCPU is not serialized (normal mode) and show cycles will be performed for all indirect
changes in the program flow
RCPU is not serialized (normal mode) and no show cycles will be performed for fetched
instructions
Figure 23-26. Development Port Data Register (DPDR)
6
5
Figure 23-25. Breakpoint Address Register (BAR)
6
7
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 23-27. ISCT_SER Bit Descriptions
7
8
The address of the load/store cycle that generated the breakpoint
8
Table 23-28. BAR Bit Descriptions
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Unaffected
SPR 630
Unaffected
SPR 159
Data
BARV
Functions Selected
Description
Development Support
LSB
23-53
LSB
31
31