ATTINY4-TSHR Atmel, ATTINY4-TSHR Datasheet - Page 88
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ATTINY4-TSHR
Manufacturer Part Number
ATTINY4-TSHR
Description
IC MCU AVR 512B FLASH SOT-23-6
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY10-TSHR.pdf
(169 pages)
Specifications of ATTINY4-TSHR
Package / Case
SOT-23-6
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
12MHz
Number Of I /o
4
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32 x 8
Program Memory Size
512B (512 x 8)
Oscillator Type
Internal
Peripherals
POR, PWM, WDT
Core Size
8-Bit
Controller Family/series
ATtiny
No. Of I/o's
4
Ram Memory Size
32Byte
Cpu Speed
12MHz
No. Of Timers
1
Rohs Compliant
Yes
Processor Series
ATTINY4x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
32 B
Interface Type
ISP
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
4
Number Of Timers
1
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
Package
6SOT-23
Device Core
AVR
Family Name
ATtiny
Maximum Speed
12 MHz
Operating Supply Voltage
2.5|3.3|5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY4-TSHR
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
88
ATtiny4/5/9/10
Figure 13-6. ADC Timing Diagram, Auto Triggered Conversion
In Free Running mode (see
conversion completes, while ADSC remains high.
Figure 13-7. ADC Timing Diagram, Free Running Conversion
For a summary of conversion times, see
Table 13-1.
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCL
Condition
First conversion
Normal conversions
Auto Triggered conversions
Prescaler
Reset
Cycle Number
ADC Clock
ADSC
ADIF
ADCL
ADC Conversion Time
Update
MUX
1
2
Figure
One Conversion
3
Sample &
11
Hold
4
13-7), a new conversion will be started immediately after the
Sample & Hold (Cycles from
5
12
Conversion complete
Table
Start of Conversion)
6
MUX update
13
13-1.
7
One Conversion
16.5
3.5
4
8
Next Conversion
1
Conversion Result
9
2
10
11
Sample & Hold
3
Conversion Time (Cycles)
12
Conversion
Complete
13
4
13.5
25
13
Prescaler
Reset
Conversion Result
8127D–AVR–02/10
Next Conversion
1
2