AT89LP214-20XU Atmel, AT89LP214-20XU Datasheet
AT89LP214-20XU
Specifications of AT89LP214-20XU
Related parts for AT89LP214-20XU
AT89LP214-20XU Summary of contents
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... Two 16-bit Enhanced Timer/Counters – Two 8-bit PWM Outputs (AT89LP213 Only) – Enhanced UART with Automatic Address Recognition and Framing Error Detection (AT89LP214 Only) – Enhanced Master/Slave SPI with Double-buffered Send/Receive – Programmable Watchdog Timer with Software Reset – Analog Comparator with Selectable Interrupt and Debouncing – ...
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... Flash memory, 128 bytes of RAM I/O lines, two 16-bit timer/counters, two PWM outputs (AT89LP213 only), a programmable watchdog timer, a full duplex serial port (AT89LP214 only), a serial peripheral interface, an internal 8 MHz RC oscillator, on-chip crystal oscillator, and a four-level, six-vector interrupt system. The two timer/counters in the AT89LP213/214 are enhanced with two new modes. Mode 0 can be configured as a variable 9- to 16-bit timer/counter and Mode 1 can be configured as a 16-bit auto-reload timer/counter ...
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Pin Description Table 3-1. AT89LP213 Pin Description Pin Symbol Type Description I/O P1.5: User-configurable I/O Port 1 bit 5. I/O MOSI: SPI master-out/slave-in. When configured as master, this pin is an output. When configured as 1 P1.5 slave, this ...
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... Table 3-2. AT89LP214 Pin Description Pin Symbol Type Description I/O P1.5: User-configurable I/O Port 1 bit 5. I/O MOSI: SPI master-out/slave-in. When configured as master, this pin is an output. When configured as 1 P1.5 slave, this pin is an input. I GPI5: General-purpose Interrupt input 5. I/O P1.7: User-configurable I/O Port 1 bit 7. ...
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... AT89LP213 Block Diagram Single Cycle 8051 CPU 2KB Flash 128 Bytes RAM Port 3 Configurable I/O Port 1 Configurable I/O General-purpose Interrupt AT89LP214 Block Diagram Single Cycle 8051 CPU 2KB Flash 128 Bytes RAM Port 3 Configurable I/O Port 1 Configurable I/O General-purpose Interrupt CPU Clock ...
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... Mode 3, the timer counts at the clock frequency and not at 1/12 the clock frequency. To maintain the same baud rate in the AT89LP214 while running at the same frequency as a standard 8051, the time-out period must be 12 times longer. Mode 1 of Timer 1 supports 16-bit auto-reload to facilitate longer time-out periods for generating low baud rates ...
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... MOVC instruction. The AT89LP213/214 does not support external program memory. Figure 6-1. 3538E–MICRO–11/10 Table 12-1 on page Program Memory Map 007F User Signature Array 0040 001F Atmel Signature Array 0000 07FF Program Memory 0000 AT89LP213/214 20). Constant tables can be allo- 7 ...
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... A map of the AT89LP213/214 program memory is shown in code space from 0000h to 07FFh, the AT89LP213/214 also supports a 64-byte User Signature Array and a 32-byte Atmel Signature Array that are accessible by the CPU in a read-only fash- ion. In order to read from the signature arrays, the SIGEN bit in AUXR1 must be set. While SIGEN is one, MOVC A,@A+DPTR will access the signature arrays ...
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Special Function Registers A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 7-1. Note that not all of the addresses are occupied, and unoccupied addresses may not be imple- mented ...
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Enhanced CPU The AT89LP213/214 uses an enhanced 8051 CPU that runs times the speed of stan- dard 8051 devices ( times the speed of X2 8051 devices). The increase in performance is ...
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... Fetch Immediate Operand 8.1 Restrictions on Certain Instructions The AT89LP213/214 is an economical and cost-effective member of Atmel's growing family of microcontrollers. It contains 2K bytes of Flash program memory fully compatible with the MCS-51 architecture, and can be programmed using the MCS-51 instruction set. However, there are a few considerations one must keep in mind when utilizing certain instructions to pro- gram this device ...
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System Clock The system clock is generated directly from one of three selectable clock sources. The three sources are the on-chip crystal oscillator, external clock source, and internal RC oscillator. The clock source is selected by the Clock Source ...
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... XTAL2 may also be configured to output a divided version of the system clock. The frequency of the oscillator may be adjusted by changing the RC Adjust Fuses. figuration Fuses” on page the Atmel SIgnature. 9.4 System Clock Out When the AT89LP213/214 is configured to use either an external clock or the internal RC oscil- lator, a divided version of the system clock may be output on XTAL2 (P3 ...
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Table 9-2. – Clock Control Register CLKREG CLKREG = 8FH Not Bit Addressable TPS3 TPS2 Bit 7 6 Symbol Function TPS3 Timer Prescaler. The Timer Prescaler selects the time base for Timer 0, Timer 1 and the Watchdog Timer. The ...
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Figure 10-1. Power-on Reset Sequence (BOD Disabled) TIME-OUT INTERNAL RESET INTERNAL RESET If the Brown-out Detector (BOD) is also enabled, the start-up timer does not begin counting until after V CC event occurs prior to the end of the initialization ...
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Table 10-1. SUT Fuse 1 10.2 Brown-out Reset The AT89LP213/214 has an on-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD is nominally ...
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Watchdog Reset When the Watchdog times out, it will generate an internal reset pulse lasting 16 clock cycles. Watchdog reset will also set the WDTOVF flag in WDTCON. To prevent a Watchdog reset, the watchdog reset sequence 1EH/E1H must ...
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The time-out period is controlled by the Start-up Timer Fuses (see 16). The interrupt pin need not remain low for the entire time-out period. Figure 11-1. Interrupt Recovery from Power-down (PWDEX = 0) PWD XTAL1 INT1 INTERNAL CLOCK When ...
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Figure 11-3. Reset Recovery from Power-down. PWD XTAL1 RST INTERNAL CLOCK INTERNAL RESET Table 11-1. – Power Control Register PCON PCON = 87H Not Bit Addressable SMOD1 SMOD0 Bit 7 6 Symbol Function SMOD1 Double Baud Rate bit. Doubles the ...
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The polling sequence is based on the vector address; an interrupt with a lower vector address has higher priority than an interrupt with a higher vector address. Note that the ...
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Interrupt Response Time The interrupt flags may be set by their hardware in any clock cycle. The interrupt controller polls the flags in the last clock cycle of the instruction in progress. If one of the flags was set ...
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Table 12-2. – Interrupt Enable Register A8H Bit Addressable EA EC Bit 7 6 Symbol Function EA Global enable/disable. All interrupts are disabled when When each interrupt source is enabled/disabled by ...
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Table 12-4. – Interrupt Priority High Register IPH IPH = B7H Not Bit Addressable – – Bit 7 6 Symbol Function PGH General-purpose Interrupt Priority High PSH Serial Port Interrupt Priority High PT1H Timer 1 Interrupt Priority High PX1H External ...
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... P1.3, P3.2 and P3.3, which may be used to wake up the device. Therefore P1.3, P3.2 and P3.3 should not be left floating during Power- down recommended that P3.1–0 on AT89LP213 and P3.4–5 on AT89LP214 be configured for either quasi-bidirectional or push-pull output mode. ...
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Figure 13-1. Quasi-bidirectional Output From Port Register 13.1.2 Input-only Mode The input only port configuration is shown in input includes a Schmitt-triggered input for improved input noise rejection. The input circuitry of P1.3, P3.2 and P3.3 is not disabled during ...
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Figure 13-4. Open-drain Output Register 13.1.4 Push-pull Output The push-pull output configuration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic “1”. ...
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Port Read-modify-write A read from a port will read either the state of the pins or the state of the port register depending on which instruction is used. Simple read instructions will always access the port pins directly. Read-modify-write ...
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... There are no restrictions on the duty cycle of the input signal, but it should be held for at least one full clock cycle to ensure that a given level is sampled at least once before it changes. In the AT89LP214, the T0 and T1 inputs are not available at the pins. AT89LP213/214 ...
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However, the inputs may be exercised in software by toggling the P3.4 and P3.5 bits in the Port 3 register. Furthermore, the Timer or Counter functions for Timer 0 and Timer 1 have four operating modes: variable width timer, 16-bit ...
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Mode 1 – 16-bit Auto-Reload Timer/Counter In Mode 1 the Timers are configured for 16-bit auto-reload. The Timer register is run with all 16 bits. The 16-bit reload value is stored in the high and low reload registers (RH1/RL1). ...
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Mode 3 – 8-bit Split Timer Timer 1 in Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two separate counters. The ...
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Table 14-2. TMOD: Timer/Counter Mode Control Register TMOD = 89H Not Bit Addressable GATE C Timer1 Gate Gating control when set. Timer/Counter x is enabled only while INTx pin is high and TRx control pin is set. When ...
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Table 14-3. – Timer/Counter Control Register B TCONB TCONB = 91H Not Bit Addressable PWM1EN PWM0EN Bit 7 6 Symbol Function PWM1EN Configures Timer 1 for Pulse Width Modulation output on T1 (P3.5). PWM0EN Configures Timer 0 for Pulse ...
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Mode 0 – 8-bit PWM with 8-bit Logarithmic Prescaler In Mode 0, TLx acts as a logarithmic prescaler driving 8-bit counter THx (see PSCx bits in TCONB control the prescaler value. On THx overflow, the duty cycle value in ...
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Figure 14-7. Timer/Counter 1 PWM Mode 1 GATE INT1 Pin Figure 14-8. Timer/Counter 1 PWM Mode 2 Note: Figure 14-9. PWM Mode 2 Waveform 3538E–MICRO–11/10 ÷TPS OSC Control TR1 ÷TPS OSC Control TR1 GATE INT1 Pin {RH0 & RL0}/{RH1 & ...
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Mode 3 – Split 8-bit PWM Timer 1 in PWM Mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in PWM Mode 3 establishes TL0 and TH0 as two separate ...
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External Interrupts When the AT89LP213/214 is configured to use the internal RC Oscillator, XTAL1 and XTAL2 may be used as the INT0 and INT1 external interrupt sources. When the external clock source is used, XTAL2 is available as INT1. ...
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Table 16-2. – General-purpose Interrupt Level Select Register GPLS GPLS = 9BH Not Bit Addressable GPLS7 GPLS6 Bit 7 6 GPMOD detect low level or negative edge on P1 detect high level or positive edge on ...
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... Serial Interface The serial interface on the AT89LP214 implements a Universal Asynchronous Receiver/Trans- mitter (UART). The UART has the following features: • Full Duplex Operation • Data Bits • Framing Error Detection • Multiprocessor Communication Mode with Automatic Address Recognition • Baud Rate Generator Using Timer 1 • ...
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The slaves that are not addressed set their SM2 bits and ignore the data bytes. The SM2 bit has no effect in Mode 0 but can be used to check ...
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Baud Rates The baud rate in Mode 0 is fixed as shown in the following equation: The baud rate in Mode 2 depends on the value of the SMOD1 bit in Special Function Register PCON.7. If SMOD1 = 0 ...
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More About Mode 0 Serial data enters and exits through RXD. TXD outputs the shift clock. Eight data bits are trans- mitted/received, with the LSB first. The baud rate is fixed at 1/2 the oscillator frequency. 17-1 on page ...
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Figure 17-1. Serial Port Mode 0 1/2 f osc WRITE TO SBUF SEND SHIFT RXD (DATA OUT) TXD (SHIFT CLOCK) TI WRITE TO SCON (CLEAR RI) RI RECEIVE SHIFT RXD (DATA IN) TXD (SHIFT CLOCK) 3538E–MICRO–11/10 INTERNAL BUS “1“ INTERNAL ...
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... Ten bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in SCON. In the AT89LP214, the baud rate is determined by the Timer 1 overflow rate. plified functional diagram of the serial port in Mode 1 and associated timings for transmit and receive. Transmission is initiated by any instruction that uses SBUF as a destination register. The “ ...
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Figure 17-2. Serial Port Mode 1 TIMER 1 OVERFLOW WRITE ÷2 TO SBUF SMOD1 SMOD1 = INTERRUPT SAMPLE 1-TO-0 TRANSITION DETECTOR RXD TX CLOCK WRITE TO SBUF SEND DATA SHIFT D0 TXD START BIT TI ÷16 RESET ...
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More About Modes 2 and 3 Eleven bits are transmitted (through TXD), or received (through RXD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmit, the 9th ...
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Figure 17-3. Serial Port Mode 2 CPU CLOCK SMOD1 1 SMOD1 0 3538E–MICRO–11/10 INTERNAL BUS INTERNAL BUS AT89LP213/214 47 ...
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Figure 17-4. Serial Port Mode 3 TIMER 1 OVERFLOW WRITE TO ÷2 SBUF SMOD1 SMOD1 = INTERRUPT SAMPLE 1-TO-0 TRANSITION DETECTOR RXD TX CLOCK WRITE TO SBUF SEND DATA SHIFT D0 D1 TXD START BIT TI STOP ...
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Framing Error Detection In addition to all of its usual modes, the UART can perform framing error detection by looking for missing stop bits, and automatic address recognition. When used for framing error detect, the UART looks for missing ...
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In a more complex system, the following could be used to select slaves 1 and 2 while excluding slave 0: Slave 0 Slave 1 Slave 2 In the above example, the differentiation among the 3 slaves is in the lower ...
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The interconnection between master and slave CPUs with SPI is shown in pins in the interface are Master-In/Slave-Out (MISO), Master-Out/Slave-In (MOSI), Shift Clock (SCK), and Slave Select (SS). The SCK pin is the clock output in master mode, but is ...
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Table 18-1. SPCR – SPI Control Register SPCR Address = E9H Not Bit Addressable SPIE SPE Bit 7 6 Symbol Function SPI interrupt enable. This bit, in conjunction with the ES bit in the IE register, enables SPI interrupts: SPIE ...
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Table 18-3. SPSR – SPI Status Register SPSR Address = E8H Not Bit Addressable SPIF WCOL Bit 7 6 Symbol Function SP interrupt flag. When a serial transfer is complete, the SPIF bit is set and an interrupt is generated ...
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Figure 18-2. SPI Shift Register Diagram Serial In Transmit Byte Figure 18-3. SPI Block Diagram ÷4÷8÷32÷64 AT89LP213/214 54 7 Serial Master 8 2 MUX LATCH CLK 8 Parallel Master (Write Buffer LATCH CLK Oscillator MSB ...
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The CPHA (Clock PHAse), CPOL (Clock POLarity), and SPR (Serial Peripheral clock Rate = baud rate) bits in SPCR control the shape and rate of SCK. The two SPR bits provide four possi- ble clock rates when the SPI is ...
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Analog Comparator A single analog comparator is provided on the AT89LP213/214. The analog comparator has the following features: • Comparator Output Flag and Interrupt • Selectable Interrupt Condition – High- or Low-level – Rising- or Falling-edge – Output Toggle ...
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Table 19-1. – Analog Comparator Control & Status Register ACSR ACSR = 97H Not Bit Addressable – – Bit 7 6 Symbol Function CIDL Comparator Idle Enable. If CIDL = 1 the comparator will continue to operate during Idle mode. ...
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Programmable Watchdog Timer The programmable Watchdog Timer (WDT) protects the system from incorrect execution by trig- gering a system reset when it times out after the software has failed to feed the timer prior to the timer overflow. By ...
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Software Reset A Software Reset of the AT89LP213/214 is accomplished by writing the software reset sequence 5AH/A5H to the WDTRST SFR. The WDT does not need to be enabled to generate the software reset. A normal software reset will ...
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Instruction Set Summary The AT89LP213/214 is fully binary compatible with the MCS-51 instruction set. The difference between the AT89LP213/214 and the standard 8051 is the number of cycles required to execute an instruction. Instructions in the AT89LP213/214 may take ...
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Table 21- Logical CLR A CPL A ANL A, Rn ANL A, direct ANL A, @Ri ANL A, #data ANL direct, A ANL direct, #data ORL A, Rn ORL A, direct ORL A, @Ri ORL A, #data ORL ...
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Table 21-1. Data Transfer MOV A, Rn MOV A, direct MOV A, @Ri MOV A, #data MOV Rn, A MOV Rn, direct MOV Rn, #data MOV direct, A MOV direct, Rn MOV direct, direct MOV direct, @Ri MOV direct, #data ...
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Table 21-1. Bit Operations CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C, bit ANL C, bit ORL C, bit ORL C, /bit MOV C, bit MOV bit, C Branching JC rel JNC rel JB ...
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On-chip Debug System The AT89LP213/214 On-chip Debug (OCD) System uses a two-wire serial interface to control program flow; read, modify, and write the system state; and program the nonvolatile memory. The OCD System has the following features: • Complete ...
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... OCD reset command should be sent to the device prior to resuming normal execution to ensure correct watchdog behavior. 23. Programming the Flash Memory The Atmel AT89LP213/214 microcontroller features 2KB of on-chip In-System Programmable Flash program memory. In-System Programming (ISP) allows programming and reprogramming of the microcontroller positioned inside the end system. Using a simple 4-wire SPI interface, the In-System programmer communicates serially with the AT89LP213/214 microcontroller, repro- gramming all nonvolatile memories on the chip ...
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Flexible Page Programming • Row Erase Capability • Page Write with Auto-Erase Commands • Programming Status Register For more detailed information on In-System Programming, refer to the Application Note entitled “AT89LP In-System Programming Specification”. 23.1 Physical Interface In-System Programming ...
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... Fuse Write with Auto-Erase command using the temporary data. Lock bits are treated in a simi- lar manner to fuses except they may only be erased (unlocked) by Chip Erase. Table 23-1. Device # AT89LP213 AT89LP214 Figure 23-2. AT89LP213/214 Memory Organization 3538E–MICRO–11/10 Code Memory Sizes Code Size ...
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Command Format Programming commands consist of an opcode byte, two address bytes, and zero or more data bytes. In addition, all command packets must start with a two-byte preamble of AAH and 55H. The preamble increases the noise immunity ...
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Figure 23-3. Command Sequence Flow Chart Figure 23-4. ISP Command Packet SS SCK MOSI Preamble 1 MISO X 3538E–MICRO–11/10 Input Preamble 1 (AAh) Input Preamble 2 (55h) Input Opcode Input Address High Byte Input Address Low Byte Input/Output Address +1 ...
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... Each byte address selects one fuse or lock bit. Data bytes must be 00h or FFh. 4. See Table 23-5 on page 72 5. See Table 23-4 on page 71 6. Atmel Signature Bytes: AT89LP213: Address AT89LP214: Address 7. Symbol Key: a: Page Address Bit b: Byte Address Bit x: Don’t Care Bit ...
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... User fuses must be programmed before enabling Lock bit mode Lock bit mode 3 imple- mented mode 2 and also blocks reads from the code memory; however, reads of the User Signature Array, Atmel Signature Array, and User Configuration Fuses are still allowed. Table 23-4. ...
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... FFh: In-System Programming Enabled 00h: In-System Programming Disabled (Enabled at POR only) Adjusts the frequency of the internal RC oscillator. A copy of the 8MHz factory setting is stored at location 0008h of the Atmel Signature. FFh: Programming of User Signature Disabled 00h: Programming of User Signature Enabled FFh: I/O Ports start in input-only mode (tristated) after reset ...
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Programming Interface Timing This section details general system timing sequences and constraints for entering or exiting In- System Programming as well as parameters related to the Serial Peripheral Interface during ISP. The general timing parameters for the following waveform ...
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ISP Start Sequence Execute this sequence to exit CPU execution mode and enter ISP mode when the device has passed Power-on Reset and is already operational. 1. Drive RST low. 2. Drive SS high. 3. Wait t 4. Start ...
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Serial Peripheral Interface The Serial Peripheral Interface (SPI byte-oriented full duplex synchronous serial communi- cation channel. During In-System programming the programmer always acts as the SPI master and the target device always acts as the SPI slave. ...
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Timing Parameters The timing parameters for are shown in Table 23-6. Symbol t CLCL t PW RUP t POR t PW RDN t RLZ t STL t RHZ t SCK t SHSL t SLSH ...
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Electrical Characteristics 24.1 Absolute Maximum Ratings* Operating Temperature ................................... -40°C to +85°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground......-0.7V to +5.5V Maximum Operating Voltage ............................................ 5.5V DC Output Current...................................................... 15.0 mA 24.2 ...
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Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as quasi-bidi- rectional (with internal pull-ups). A square wave generator with rail-to-rail output ...
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Supply Current (External Clock) Figure 24-3. Active Supply Current vs. Frequency Figure 24-4. Idle Supply Current vs. Frequency 3538E–MICRO–11/10 Active Supply Current vs. Frequency External Clock Source ...
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Internal Oscillator Frequency Figure 24-5. Internal Oscillator Frequency vs. VCC Table 24-1. Typical Internal Oscillator Behavior Symbol Parameter Relative Frequency Error Δf IRC (MAX–MIN) / (MAX+MIN) Frequency f IRC (Calibrated at 25°C; 5V) Note: The data in this table ...
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Quasi-Bidirectional Output Figure 24-6. Quasi-Bidirectional Output I-V Characteristic at 5V Figure 24-7. Quasi-Bidirectional Output I-V Characteristic at 3V 3538E–MICRO–11/10 I/O DC Source Current vs. Output Voltage (VCC = 5V 2.0 2.5 3.0 3.5 0 -20 -40 -60 ...
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Push-Pull Output Figure 24-8. Push-Pull Output I-V Characteristic at 5V Figure 24-9. Push-Pull Output I-V Characteristic at 3V Note: AT89LP213/214 82 I/O DC Source Current vs. Output Voltage (VCC = 5V) V OH1 ...
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Crystal Oscillator Figure 24-10. Quartz Crystal Input at 5V Figure 24-11. Ceramic Resonator Input at 5V 3538E–MICRO–11/10 Oscillator Amplitude vs. Frequency Quartz Crystal with R1 = 4MΩ Frequency (MHz) Oscillator ...
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Clock Characteristics Figure 24-12. External Clock Drive Waveform Table 24-2. External Clock Parameters Symbol Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t External Clock High Time CHCX t External Clock Low Time CLCX t External Clock Rise ...
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Serial Peripheral Interface Timing Table 24-4. SPI Master Characteristics Symbol Parameter t Oscillator Period CLCL t Serial Clock Cycle Time SCK t Clock High Time SHSL t Clock Low Time SLSH t Rise Time SR t Fall Time SF ...
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Figure 24-13. SPI Master Timing (CPHA = 0) SS SCK (CPOL = 0) SCK (CPOL = 1) MISO MOSI Figure 24-14. SPI Slave Timing (CPHA = 0) SS SCK (CPOL = 0) SCK (CPOL= 1) MISO MOSI Figure 24-15. SPI ...
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Figure 24-16. SPI Slave Timing (CPHA = 1) SS SCK (CPOL = 0) SCK (CPOL = 1) MISO MOSI 24.6 Serial Port Timing: Shift Register Mode Test Conditions The values in this table are valid for V Symbol Parameter t ...
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Test Conditions 24.7.1 AC Testing Input/Output Waveform Note Inputs during testing are driven min. for a logic “1” and V IH (1) 24.7.2 Float Waveform Note: 1. For timing purposes, a port pin is ...
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I Test Condition, Active Mode, All Other Pins are Disconnected CC 24.7.4 I Test Condition, Idle Mode, All Other Pins are Disconnected CC 24.7.5 Clock Signal Waveform for 0.5V CC 0.45V 24.7.6 I Test Condition, Power-down ...
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... Green Package Option (Pb/Halide-free) Speed Power (MHz) Supply Ordering Code AT89LP213-20PU AT89LP213-20XU 20 2.4V to 5.5V AT89LP214-20PU AT89LP214-20XU 14P3 14-lead, 0.300” Wide, Plastic Dual In-line Package (PDIP) 14X 14-lead, 0.173” Wide, Plastic Thin Shrink Small Outline Package (TSSOP) AT89LP213/214 90 Package 14P3 14X 14P3 ...
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Packaging Information 26.1 14P3 – PDIP A SEATING PLANE Notes: 1. This package conforms to JEDEC reference MS-001, Variation AA. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion ...
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TSSOP Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. JEDEC Standard MO-153 AB-1. 0.65 (.0256) BSC 2325 Orchard Parkway San Jose, CA 95131 R AT89LP213/214 92 PIN 1 4.50 (0.177) 4.30 (0.169) 5.10 (0.201) 1.20 (0.047) MAX ...
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Revision History Revision No. Revision A – July 2006 Revision B – Nov. 2007 Revision C – June 2008 Revision D – Oct. 2009 Revision E – Nov. 2010 3538E–MICRO–11/10 History • Initial Preliminary Release • Removed “Preliminary” status ...
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AT89LP213/214 94 3538E–MICRO–11/10 ...
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... Memory Organization .............................................................................. 7 7 Special Function Registers ..................................................................... 9 8 Enhanced CPU ....................................................................................... 10 9 System Clock ......................................................................................... 12 10 Reset ....................................................................................................... 14 3538E–MICRO–11/10 2.1 AT89LP213: 14-lead TSSOP/PDIP ...................................................................2 2.2 AT89LP214: 14-lead TSSOP/PDIP ...................................................................2 5.1 System Clock .....................................................................................................6 5.2 Instruction Execution with Single-cycle Fetch ...................................................6 5.3 Interrupt Handling ..............................................................................................6 5.4 Timer/Counters ..................................................................................................6 5.5 Serial Port ..........................................................................................................6 5.6 Watchdog Timer ...
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Table of Contents (Continued) 11 Power Saving Modes ............................................................................. 17 12 Interrupts ................................................................................................ 19 13 I/O Ports .................................................................................................. 23 14 Enhanced Timer/Counters .................................................................... 28 15 External Interrupts ................................................................................. 37 16 General-purpose Interrupts .................................................................. 37 17 Serial Interface ....................................................................................... 39 18 ...
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Table of Contents (Continued) 20 Programmable Watchdog Timer ........................................................... 58 21 Instruction Set Summary ...................................................................... 60 22 On-chip Debug System ......................................................................... 64 23 Programming the Flash Memory .......................................................... 65 24 Electrical Characteristics ...................................................................... 77 25 Ordering Information ............................................................................. 90 26 ...
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